Datasheet
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ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
AC SWITCHING CHARACTERISTCS
bq2022A
SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range unless otherwise noted
(1)
UNIT
V
PU
DC voltage applied to data – 0.3 V to 7 V
I
OL
Low-level output current 40 mA
ESD IEC 61000-4-2 Air discharge Data to V
SS,
V
SS
to data 15 kV
T
A
Operating free-air temperature range – 20 ° C to 70 ° C
T
A(Comm)
Communication free-air temperature range Communication is specified by design – 40 ° C to 85 ° C
T
stg
Storage temperature range – 55 ° C to 125 ° C
Lead temperature (soldering, 10 s) 260 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
= – 20 ° C to 70 ° C; V
PU(min)
= 2.65 V
DC
to 5.5 V
DC
, all voltages relative to VSS
PARAMETER TEST CONDITION MIN TYP MAX UNIT
I
DATA
Supply current V
PU
= 5.5 V 20 μ A
Logic 0, V
PU
= 5.5 V, I
OL
= 4 mA, SDQ pin 0.4
V
OL
Low-level output voltage V
Logic 0, V
PU
= 2.65 V, I
OL
= 2 mA 0.4
V
OH
High-level output voltage Logic 1 V
PU
5.5
I
OL
Low-level output current (sink) V
OL
= 0.4 V, SDQ pin 4 mA
V
IL
Low-level input voltage Logic 0 0.8 V
V
IH
High-level input voltage Logic 1 2.2 V
V
PP
Programming voltage 11.5 12 V
T
A
= – 20 ° C to 70 ° C; V
PU(min)
= 2.65 V
DC
to 5.5 V
DC
, all voltages relative to VSS
PARAMETER TEST CONDITION MIN TYP MAX UNIT
t
c
Bit cycle time
(1)
60 120 μ s
t
WSTRB
Write start cycle
(1)
1 15 μ s
t
WDSU
Write data setup
(1)
t
WSTRB
15 μ s
t
WDH
Write data hold
(1) (2)
60 t
c
μ s
1
t
rec
Recovery time
(1)
μ s
For memory command only 5
t
RSTRB
Read start cycle
(1)
1 13 μ s
t
ODD
Output data delay
(1)
t
RSTRB
13 μ s
t
ODHO
Output data hold
(1)
17 60 μ s
t
RST
Reset time
(1)
480 μ s
t
PPD
Presence pulse delay
(1)
15 60 μ s
t
PP
Presence pulse
(1)
60 240 μ s
t
EPROG
EPROM programming time 2500 μ s
t
PSU
Program setup time 5 μ s
(1) 5-k Ω series resistor between SDQ pin and V
PU
. (See Figure 1 )
(2) t
WDH
must be less than t
c
to account for recovery.
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