Datasheet
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t
WSTRB
t
WDSU
t
WDH
t
rec
V
PU
V
IH
V
IL
Write ”1”
Write ”0”
READ
t
RSTRB
t
ODD
t
ODHO
t
REC
V
PU
V
IH
V
IL
Read ”1”
Read ”0”
PROGRAM PULSE
V
PP
V
PU
V
SS
t
PREC
t
PSU
t
EPROG
t
PRE
t
PFE
IDLE
CRC Generation
bq2022A
SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007
Figure 14. Write Bit Timing Diagram
The READ bit timing diagram in Figure 15 shows that the host initiates the transmission of the bit by issuing the
t
RSTRB
portion of the bit. The bq2022A then responds by either driving the DATA bus low to transmit a READ 0 or
releasing the DATA bus to transmit a READ 1.
Figure 15. Read Bit Timing Diagram
Figure 16. Program Pulse Timing Diagram
If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in
IDLE. Bus transactions can resume at any time from the IDLE state.
The bq2022A has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can
compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the
bq2022A to determine if the ROM data has been received error-free by the bus master. The equivalent
polynomial function of this CRC is: X
8
+ X
5
+ X
4
+1.
Under certain conditions, the bq2022A also generates an 8-bit CRC value using the same polynomial function
just shown and provides this value to the bus master to validate the transfer of command, address, and data
bytes from the bus master to the bq2022A. The bq2022A computes an 8-bit CRC for the command, address, and
data bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to
the bus master to confirm proper transfer. Similarly, the bq2022A computes an 8-bit CRC for the command and
address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/
GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC
generator on the bq2022A is also used to provide verification of error-free data transfer as each page of data
from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command,
and for the eight bytes of information in the status memory field.
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