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FEATURES DESCRIPTION

APPLICATIONS

DBZP

bq2022A

ACKAGE

(TOP VIEW)

SDQ

VSS

IDROM

(64bits)

EPROM

MEMORY

(1024bits)

EPROM

STATUS

(64bits)

SDQCommunications

Controllerand8-BitCRC

GenerationCircuit

Internal

Bus

RAM

Buffer

(8bytes)

SDQ 1

2VSS 3 VSS

SDQ

VSS

LP PACKAGE

(BOTTOMVIEW)

bq2022A

SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007

www.ti.com

1K-BIT SERIAL EPROM WITH SDQ INTERFACE

• 1024 bits of One-Time Programmable (OTP)

The bq2022A is a 1K-bit serial EPROM containing a

EPROM For Storage Of User-Programmable

factory-programmed, unique 48-bit identification

Configuration Data

number, 8-bit CRC generation, and the 8-bit family

code (09h). A 64-bit status register controls write

• Factory-Programmed Unique 64-Bit

protection and page redirection.

Identification Number

The bq2022A SDQ™ interface requires only a single

• Bus-Interface Architecture Allowing Multiple

connection and a ground return. The DATA pin is

bq2022As Attached to a Single Host

also the sole power source for the bq2022A. The bus

• Single-Wire Interface to Reduce Circuit Board

architecture allows multiple SDQ devices to be

Routing

connected to a single host.

• Synchronous Communication Reduces Host

The small surface-mount package options saves

Interrupt Overhead

printed-circuit-board space, while the low cost makes

• 15KV IEC 61000-4-2 ESD Compliance on Data

it ideal for applications such as battery pack

configuration parameters, record maintenance, asset

tracking, product-revision status, and access-code

• No Standby Power Required

security.

• Available in a 3-Pin SOT23 Package and

TO-92 Package

ORDERING INFORMATION

(1)

PACKAGED DEVICES

(3)

(2)

PART NUMBER PACKAGE STATUS

• Security Encoding

bq2022ADBZR SOT23-3 Production

• Inventory Tracking

– 20 ° C to 70 ° C

bq2022ALPR TO-92 Production

• Product-Revision Maintenance

(1) For the most current package and ordering information, see

• Battery-Pack Identification

the Package Option Addendum at the end of this document, or

see the TI Web site at www.ti.com

(2) Device specified to communicate at – 40 ° C to 85 ° C

(3) The device is available only in tape and reel with a base

quantity of 3000 units for the bq2022ADBZR and 2000 units for

the bq2022ALPR.

BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SDQ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
bq2022A www.ti.
PAGE 2
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VPU DC voltage applied to data IOL Low-level output current –0.
PAGE 3
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 AC SWITCHING CHARACTERISTCS (continued) TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS PARAMETER TEST CONDITION MIN TYP MAX UNIT μs tPREC Program recovery time 5 tPRE Program rising-edge time 5 μs tPFE Program falling-edge time 5 μs tRSTREC 480 μs Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION bq2022ADBZR SDQ 1 I Data VSS 2, 3 - Ground.
PAGE 4
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 EPROM STATUS MEMORY In addition to the programmable 1024-bits of memory are 64 bits of status information contained in the EPROM STATUS memory. The STATUS memory is accessible with separate commands. The STATUS bits are EPROM and are read or programmed to indicate various conditions to the software interrogating the bq2022A.
PAGE 5
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 VPU bq2022 A SDQ SDQI 1 Communications Controller CPU SDQO VSS 2 VSS 3 HOST Figure 1. Typical Applications Circuit Serial Communication A host reads, programs, or checks the status of the bq2022A through the hierarchical command structure of the SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or status can be read or modified.
PAGE 6
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 MATCH ROM The MATCH ROM command, 55h, is used by the host to select a specific SDQ device when the family code and identification number is known. The host issues the MATCH ROM command followed by the family code, ROM number, and the CRC byte. Only the device that matches the 64-bit ROM sequence is selected and available to perform subsequent Memory/Status Function commands.
PAGE 7
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 SKIP ROM This SKIP ROM command, CCh, allows the host to access the memory/status functions without issuing the 64-bit ROM code sequence. The SKIP ROM command is directly followed by a memory/status functions command. Because this command can cause bus collisions when multiple SDQ devices are on the same bus, this command should be issued in single device applications.
PAGE 8
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 READ MEMORY/Field CRC To read memory without CRC generation on 32-byte page boundaries, the ROM command is followed by the READ MEMORY command, F0h, followed by the address low byte and then the address high byte. NOTE: As shown in Figure 8, individual bytes of address and data are transmitted LSB first.
PAGE 9
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 For both of these cases, the decision to continue programming is made entirely by the host, because the bq2022A is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-bit CRC calculated by the bq2022A. Prior to programming, bits in the 1024-bit EPROM data field appear as logical 1s.
PAGE 10
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 READ STATUS The READ STATUS command is used to read data from the EPROM status data field. After issuing a ROM command, the host issues the READ STATUS command, AAh, followed by the address low byte and then the address high byte. NOTE: An 8-bit CRC of the command byte and address bytes is computed by the bq2022A and read back by the host to confirm that the correct command word and starting address were received.
PAGE 11
bq2022A www.ti.
PAGE 12
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 After the programming pulse is applied and the data line returns to VPU, the host issues eight read time slots to verify that the appropriate bits have been programmed. The bq2022A responds with the data from the selected EPROM STATUS address sent least significant bit first. This response should be checked to verify the programmed byte.
PAGE 13
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 PROGRAM PROFILE BYTE The PROGRAM PROFILE byte is read to determine the WRITE MEMORY programming sequence required by a specific manufacturer. After issuing a ROM command, the host issues the PROGRAM PROFILE BYTE command, 99h. Figure 12 shows the the bq2022A responds with 55h. This informs the host that the WRITE MEMORY programming sequence is the one described in the WRITE MEMORY command section of this data sheet.
PAGE 14
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 V PU Write ”1” V IH V IL Write ”0” t rec t WSTRB t WDSU t WDH Figure 14. Write Bit Timing Diagram READ The READ bit timing diagram in Figure 15 shows that the host initiates the transmission of the bit by issuing the tRSTRB portion of the bit. The bq2022A then responds by either driving the DATA bus low to transmit a READ 0 or releasing the DATA bus to transmit a READ 1.
PAGE 15
bq2022A www.ti.com SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007 In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the bq2022A (for ROM reads) or the 8-bit CRC value computed within the bq2022A.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ2022ADBZR Package Package Pins Type Drawing SPQ SOT-23 3000 DBZ 3 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 179.0 8.4 Pack Materials-Page 1 3.15 B0 (mm) K0 (mm) P1 (mm) 2.95 1.22 4.0 W Pin1 (mm) Quadrant 8.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ2022ADBZR SOT-23 DBZ 3 3000 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.