Datasheet

The CI values are:
Where CI is:
0 When LMD is updated with a valid full dis
-
charge
1 After the 64th valid charge action with no
LMD updates or when the device is reset
The valid discharge flag (VDQ) is asserted when the
bq2014 is discharged from NAC = LMD or DONE is
valid. The flag remains set until either LMD is updated
or one of three actions that can clear VDQ occurs:
n
The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.
n
A valid charge action sustained at V
SRO
> V
SRQ
for at
least 256 NAC counts.
n
The EDV flag was set at a temperature below 0°C
The VDQ values are:
Where VDQ is:
0 SDCR
≥
4096, subsequent valid charge ac
-
tion detected, or EDV1 is asserted with the
temperature less than 0°C
1 On first discharge after NAC = LMD or
DONE is valid
The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG
1
, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is immi
-
nent. The EDV1 flag is latched until a valid charge has
been detected. The EDV1 threshold is externally con
-
trolled via the VTS register (see Voltage Threshold Reg
-
ister on this page).
The EDV1 values are:
Where EDV1 is:
0 Valid charge action detected,V
SB
≥ V
TS
1V
SB
< V
TS
providing that OVLD=0 (see
FLGS2 register description)
The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condi
-
tion. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EMPTY pin is also forced to a high-impedance state on
assertion of EDVF. The host system may pull EMPTY
high, which may be used to disable circuitry to prevent
deep-discharge of the battery. The EDVF threshold is
set 100mV below the EDV1 threshold.
The EDVF values are:
Where EDVF is:
0 Valid charge action detected,
V
SB
≥ V
TS
- 100mV
1V
SB
<V
TS
- 100mV providing that OVLD=0
(see FLGS2 register description)
Voltage Threshold Register (VTS)
The end-of-discharge threshold voltages (EDV1 and
EDVF) can be set using the VTS register (address=0ch).
The read/write VTS register sets the EDV1 trip point.
EDVF is set 100mV below EDV1. The default value in
the VTS register is 70h, representing EDV1 = 1.05V and
EDVF = 0.95V. EDV1 = 2.4V ∗ (VTS/256).
Battery Voltage Register (VSB)
The read-only battery voltage register is used to read
the single-cell battery voltage on the SB pin. The VSB
register is updated approximately once per second with
the present value of the battery voltage.
V
SB
= 2.4V ∗ (VSB/256)
12
bq2014
VSB Register Bits
76543210
VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0
FLGS1 Bits
76543 2 1 0
- - - - VDQ - - -
FLGS1 Bits
7654 3 2 1 0
- - - - - - EDV1 -
FLGS1 Bits
76543 2 1 0
---CI- - - -
FLGS1 Bits
7654 3 2 1 0
---- - - -EDVF
VTS Register Bits
76543210
VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0