Datasheet

AMC7823
SLAS453F –APRIL 2005–REVISED MARCH 2012 www.ti.com
ALR Register (see Figure 53)
Bit 15 Bit 0
MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
X X X X ALR-3 ALR-2 ALR-1 ALR-0 X X X X 0 0 0 0
X : Don't Care
The first four analog inputs in the group defined by bits [SA3:SA0] and [EA3:EA0] in the ADC Control Register
are implemented with out-of-range detection.
[Bit 3:Bit 0] Must be '0' to ensure correct operation of alarm detection.
ALR-n (READ-ONLY) nth analog input out-of-range status flag. These bits are read-only. Writing ALR-n
bits has no effect.
ALR-n = '1' when the nth analog input is out-of-range.
ALR-n = '0' when the nth analog input is not out-of-range. ALR-n is always '0' when
following conditions hold: the value of Threshold-Low-n Register is equal to '0', and
the Threshold-Hi-n Register is equal to the full-scale value of the input.
NOTE: To avoid loss of alarm data during power-down of the ADC, change to direct conversion mode (see ADC
Control Register) before power-down and do not issue a convert command while the ADC is powered down.
After power-on or reset, all bits in ALR Register are cleared to '0'. Reading the register does not clear any bits.
GPIO Register (Read/Write; see the Digital I/O section)
The AMC7823 has six general-purpose I/O (GPIO) pins to communicate with external devices. Pins GPIO-4 and
GPIO-5 are dedicated to general bidirectional, digital I/O signals. The remaining pins (n = 0, 1, 2, 3) are dual-
purpose and can be programmed as either GPIO pins or ALR (out-of-range) indicators. This register defines the
status of all GPIO pins and the functions of pins GPIO-0, GPIO-1, GPIO-2 and GPIO-3. The register is formatted
as shown here.
Bit 15 Bit 0
MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
1 1 1 1 IOMO IOMO IOMO IOMO 1 1 IOST5 IOST4 IOST3 IOST2 IOST1 IOST0
D3 D2 D1 D0
IOMOD-n Function mode definition bit for pins GPIO-0, GPIO-1, GPIO-2, and GPIO-3 (see Table 8
and Figure 52)
IOMOD-n = 0 Analog input out-of-range detection mode. In this mode, GPIO-n (n = 0, 1, 2, 3) work as
analog input out-of-range indicators, denoted as output pins ALR-n. The status of each pin
ALR-n is set by bit ALR-n of the ALR Register. The ALR-n pin is low when the
corresponding ALR-n bit is '1', and is high-impedance when ALR-n is '0'.
IOMOD-n = 1 GPIO mode. In this mode, pin GPIO-n works as general digital I/O (bidirectional). When
the pin is output, the status is determined by the corresponding bit IOST-n; it is high-
impedance for IOST-n = 1, and logic low for IOST-n = 0. When the pin is input, reading
this bit acquires the digital logic value present at the pin. GPIO data are preserved during
all power-down conditions.
IOST-n I/O STATUS bit of the GPIO-n pin. If the GPIO-n pin works as a general-purpose I/O, this
bit indicates the actual logic value present at the pin when reading the bit. It also sets the
state of the corresponding GPIO-n pin (high-impedance for IOST-n = 1, logic low for
IOST-n = 0) when writing to the bit. An external pull-up resistor is required when using pin
GPIO-n as an output.
If the GPIO-n pin works as an analog input out-of-range indicator, then bit IOST-n is a
complement of the corresponding bit ALR-n in the ALR Register. Writing the IOST-n bit
does not cause any change. Note that only GPIO-0, GPIO-1, GPIO-2, and GPIO-3 can be
configured as out-of-range indicators.
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