Datasheet

AMC7823
www.ti.com SLAS453F –APRIL 2005–REVISED MARCH 2012
DAC-n Data Registers (n = 0, 1, 2, 3, 4, 5, 6, 7) (see the DAC Operation section)
This register is the input Data Register for DAC-n that buffers the DAC-n Latch Register. The DAC-n output is
updated only when Latch is loaded. Under an asynchronous load (bit SLDA-n = '0' in the DAC Configuration
Register), the value of the DAC-n Data Register is transferred into the Latch immediately after Data Register is
written. If a synchronous load is specified (SLDA-n = '1'), then the DAC-n Latch is loaded with the value of the
DAC-n Data Register only after a synchronous load signal occurs. This signal can be either the internal ILDAC or
the rising edge of an external ELDAC (see DAC Operation and DAC Configuration Register discussions).
Bit 15 Bit 0
MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
X OCH2 OCH1 OCH0 DAC1 DAC1 DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
1 0
X : Don't Care
DAC11–DAC0 In a write operation, these data bits are written into the DAC Data-n Register. However, in
(WRITE/READ) a read operation, the data bits are returned from the DAC-n Latch, not from the DAC-n
Data Register.
OCH2–OCH0 DAC Address. Read-only. Writing these bits does not cause any change.
The registers are cleared to '0' after power-on or reset. Table 15 summarizes the DAC-n Data Registers.
Table 15. DAC-n Data Registers
OCH2 OCH1 OCH0 ANALOG OUTPUT
0 0 0 DAC0
0 0 1 DAC1
0 1 0 DAC2
0 1 1 DAC3
1 0 0 DAC4
1 0 1 DAC5
1 1 0 DAC6
1 1 1 DAC7
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