Datasheet
GPIO-n
ENABLE
BitALR-nofALRRegister
BitIOMOD-
inGPIORegister
n
IOMOD- =0, - Pinn nALR
IOMOD- =1,DigitalI/OPinn
BitIOST-
inGPIORegister
n
BitIOST-
(whenreading)
n
+
−
+
−
ALR-0
Threshold-Hi-
Register
(UpperBound)
n
GALR Pin
BitALR- of
ALRRegister
n
Threshold-Low-
Register
(LowerBound)
n
nth Analog
Input
ALR-1
ALR-2
ALR-3
ALR- isalways ‘0’ when
Threshold-Low- isequalto0
andThreshold-Hi- isequalto
full-scaleofinput
n
n
n
AMC7823
SLAS453F –APRIL 2005–REVISED MARCH 2012
www.ti.com
Figure 52. Pin Structure of GPIO-0, GPIO-1, GPIO-2, and GPIO-3
ANALOG INPUT OUT-OF-RANGE ALARM (See ADC Operation)
The AMC7823 provides out-of-range detection for the first four analog inputs of the group of inputs specified by
the starting and ending addresses [SA3:SA0] and [EA3:EA0], respectively. Figure 53 describes the analog out-of-
range logic. Alarm bits ALR-n in the ALR Register are set to '1' to flag an out-of-range condition. If the nth analog
input is out of the preset range, then bit ALR-n is set to '1'. The nth alarm bit does not necessarily correspond to
input channel address n, however. For example, if [SA3:SA0] and [EA3:EA0] of the ADC Control Register are
0x04 and 0x07, respectively, then the channel address of the first analog input is [0x04] and the corresponding
alarm bit is ALR-0. The address of the fourth input channel is [0x07] and its corresponding alarm bit is ALR-3.
Only the first four analog inputs can be implemented with out-of-range detection. In this example, the addresses
of the first four inputs implemented with out-of-range detection are [0x04], [0x05], [0x06], and [0x07],
respectively. However, if [SA3:SA0] is equal to [0x00] and [EA3:EA0] is equal to [0x07], then the addresses of
the first four are [0x00], [0x01], [0x02] and [0x03].
NOTE: Threshold-Hi-n must not be smaller than Threshold-Low-n. Otherwise, ALR-n is always '1'.
Figure 53. Analog Out-of-Range Alarm Logic
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Product Folder Link(s): AMC7823