Datasheet

AMC7823
SLAS453F –APRIL 2005–REVISED MARCH 2012 www.ti.com
The DAC synchronous load signal can be the rising edge of the external signal ELDAC, or the internal signal
ILDAC. Write BB00h into the Load DAC Register to generate ILDAC. When the DAC synchronous load signal
occurs, all DACs with the bit SLDA-n set to '1' are updated simultaneously with the value of the corresponding
DAC-n Data register. By setting the bit SLDA-n properly, several DACs can be updated at the same time. For
example, to update DAC0 and DAC1 synchronously, the host sets the bits SLDA-0 and SLDA-1 to '1' first, then
writes the proper values into the DAC-0 Data and DAC-1 Data registers, respectively. After this presetting, the
host activates ELDAC (or ILDAC) to load DAC0 and DAC1 simultaneously. The outputs of DAC0 and DAC1
change at the same time.
Table 5 summarizes methods to update the output of DAC-n.
Table 5. DAC-n Output Update Summary
WRITING LOAD EXTERNAL
BIT SLDA-n DAC REGISTER ELDAC SIGNAL OPERATION
0 Don't care Don't care Update DAC-n individually.
DAC-n Latch and DAC-n Output are immediately updated after writing to DAC-n
Data Register
1 Write 0xBB00 0 Simultaneously update all DAC by internal trigger .
Writing 0xBB00 generates internal load DAC trigger signal ILDAC, which causes
DAC-n Latches and DAC-n Outputs to be updated with the contents of
corresponding DAC-n Data Register.
1 No Rising edge Simultaneously update all DACs by external trigger ELDAC.
Rising edge of ELDAC causes DAC-n Latches and DAC-n Outputs to be
updated with the contents of corresponding DAC-n Data Register.
Full-Scale Output Range
The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain
of the DAC output buffer, V
REF
× Gain. The bit GDAC-n (Gain of DAC-n output buffer) of the DAC Configuration
Register sets the gain of the individual DAC-n output buffer. The gain is unity (1) when GDAC-n is cleared to '0',
and is 2 when GDAC-n is set to '1'.
The value of V
REF
may be controlled by bits SREF and GREF in the AMC Status/Configuration Register and by
the choice of internal or external reference. For a similar description, see the Full-Scale Range of Analog Input in
the ADC Operation section.
Full-scale output range of each DAC is limited by the analog power supply because the DAC output buffer
cannot exceed AV
DD
. Table 6 shows how to configure the DAC output range.
Table 6. Configuration of DAC Output Range
OUTPUT RANGE
SREF GREF GDAC-n REFERENCE AV
DD
= 3V AV
DD
= 5V
0 0 0 Internal 1.25V 0V to 1.25V 0V to 1.25V
0 0 1 Internal 1.25V 0V to 2.5V 0V to 2.5V
0 1 0 Internal 2.5V 0V to 2.5V 0V to 2.5V
0 1 1 Internal 2.5V Saturated at 3V 0V to 5V
Don't 0V to External V
REF
, 0V to External V
REF
,
1 0 External V
REF
care External V
REF
≤ AV
DD
External V
REF
≤ AV
DD
Don't 0V to External V
REF
× 2 0V to External V
REF
× 2
1 1 External V
REF
care 2 × External V
REF
≤ AV
DD
2 × External V
REF
≤ AV
DD
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