Datasheet

DAC-0
Data
Datafrom
Host
DAC-0
Latch
DAC-0
BitGDAC-0
(DACConfigurationRegister)
DAC-7
BitSLDA- ofDACConfigurationRegisterdetermines
whenDAC-n Latchisloadedwiththevalueof
DAC-nDataRegister.
n
Gain=2ifGDAC-0=1
Gain=1ifGDAC-0=0
V
OUT0
V Range:0 V xGain
OUT REF
-
BitPDAC-0
(Power-DownbitinPower-Down
Register;see(1))
DatatoHost
whenRead
ExternalELDAC
InternalILDACBB00h
DAC-7
Data
BitGDAC−7
Synchronous
LoadingSignal
BitPDAC-7(Power-Downbit
inPower-DownRegister)
5kW
SLDA- =1:LatchisloadedwhenSynchronous
Loadingsignaloccurs;synchronousloading
n
SLDA- =0:Latchisloadedimmediatelyafter
DAC- Dataregisteriswritten;asynchronousloading
n
n
LoadDAC
Register
LoadsallDAC- latcheswhencorrespondingSLDA- issetto ‘1’.
DoesnotaffectDAC- whenSLDA- isclearedto ‘0’.n n
n n
AMC7823
www.ti.com SLAS453F –APRIL 2005–REVISED MARCH 2012
DAC OPERATION (see DAC-n Data Registers and DAC Configuration Register)
AMC7823 has eight double-buffered DACs. The outputs of the DACs can be updated synchronously or
individually (asynchronously). Figure 47 illustrates the generic DAC structure.
(1) When PDAC-n = 0, DAC-n is in power-down mode; the output buffer of DAC-n connects to ground through a 5kΩ
load.
Figure 47. DAC Structure
Double-Buffered Data Register
All eight DAC data registers are double-buffered. Each DAC has an internal latch preceded by an input register.
Data are initially written to an individual DAC-n Data register and then transferred to its corresponding DAC-n
Latch. When the DAC-n Latch is updated, the output of DAC-n changes to the newly set value. When the host
reads the register memory map location labeled DAC-n Data, the value held in the DAC-n Latch is returned (not
the value held in the input DAC-n Data Register).
Synchronous Load, Asynchronous Load, and Output Updating
The DAC latches can be updated synchronously or asynchronously. The bit SLDA-n (Synchronous Load) of the
DAC Configuration Register is used to specify the DAC updating mode.
Asynchronous mode is active when SLDA-n is cleared to '0'. Immediately after writing to the DAC-n Data
Register, its data are transferred to the corresponding DAC-n Latch Register, and the output of DAC-n changes
accordingly.
Synchronous mode is selected when the bit SLDA-n is set to '1'. The value of the DAC-n Data Register is
transferred to the DAC-n Latch only after an active DAC synchronous loading signal occurs, which immediately
updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n Data Register
changes only the value in that register, but not the content of DAC-n Latch nor the output of DAC-n, until the
synchronous load signal occurs.
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