Datasheet

Yes
No
No
No
(2)
No
[ADR]+1
Yes
(3)
Direct-Mode
ADCinidle
Waitingnewtrigger
Auto-Mode,
InternalTriggeronly
SetDAVFbit;
Auto-Mode
(4)
Update ADC-n
DataRegister
Yes
Yes
NewADCConversionTrigger
ClearDAVFbitinAMC
Status/ConfigurationRegister
ClearallALR- inALRRegistern
Set[ADR]=[SA]
(1)
Sample
Convert
Update ADC- TMPRYn Register
Firstfourchannels?
Out-of-range?
[ADR]>[EA]?
(1)
Drive PinLowGALR
SetALR- BitinALRRegistern
Apply2- sPulse(Low)
toPin
m
DAV
Drive PinLowDAV
AMC7823
www.ti.com SLAS453F –APRIL 2005–REVISED MARCH 2012
The bit GREF in the AMC Status/Configuration Register selects between two preset internal reference values.
When GREF = '0' (power-up default condition), the internal reference is set to 1.25V. When GREF = '1', the
internal reference is 2.5V. GREF must be cleared to '0' when the power supply is less than 5V.
When an external reference is applied, the input range is 0 to 2 × V
REF
, and is not affected by the bit GREF. In
this case, ideally SREF has been set to '1' and the internal reference is disconnected. This condition is preferred
for operating the AMC7823. If SREF = '0', the external reference overrides the internal reference, provided it can
accommodate a 10kΩ load. To avoid input saturation, the external reference must not be greater than 2.5V when
the analog power supply is 5V, and must not be greater than 1.25V when the supply is 3V.
Figure 45 illustrates the ADC operation.
(1) [SA] represents the first input channel, [EA] represents the last input channel. [ADR] represents the current input
channel. [SA3:SA0] is the address of [SA]. [EA3:EA0] is the address of [EA].
(2) GALR pin goes high and bits ALR-n are cleared after new ADC Conversion trigger.
(3) After reading the ADC Data Register, bit DAVF is cleared, and the DAV pin goes high.
(4) In Auto-mode, bit DAVF is always cleared.
Figure 45. ADC Operation Flow Chart
Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): AMC7823