Datasheet
ADC−0
TMPRY
ADC−0
DATA
ADC
CH0
CH3
CH7
MUX
Double-Buffered
ADCDataRegister
AfterconversionofCH- finished,n
ADC- TMPRYregisterisupdatedn
immediately.
TMPRYregisterisatemporaryregister.
All
ADC- DAn
TA registersare
updatedsimultaneouslywhenthe
conversionofthelastchannel
selectediscompleted.(1)
CMODof ADCControl Registerdefines
conversionmode.
ForDirect-Mode(CMOD=0),eachchannel
beingconvertedisaccessedonetimeafter
triggered.
For Auto-Mode(CMOD=1),allchannels
beingconvertedareaccessedrepeatedly
aftertriggered.
ExternaltriggerworksinDirect-Modeonly.
BitECNVTof AMCStatusandConfigurationRegister
selectsthetriggersignal.
ECNVT=1,RisingEdgeofExternalCONVERTtriggersADC
ECNVT=0,WritingADCControlRegistertriggersADC
BitDAVF,Pin DAV
BitDAVFandPin indicatenewdataavailable.DAV
ADC−6
TMPRY
ADC−6
DATA
Out-of-Range Alarmof
firstfourinputsbeing
converted
CONVERT,External
InternalTriggergeneratedby
WritingADCControlRegister
BitECNVT
BitGREF,effectivefor
InternalReferenceonly
(2)
ToShifter
Register
ToShift
Register
ADC−7
TMPRY
ADC−7
DATA
ADC−8
TMPRY
ADC−8
DATA
CH8
(temperature)
0
1
Out-of-Range
ALARM
AfterADC- DataareUpdated,DAn VFissetto ‘1’.
Pin GoesLow(Direct-Mode)orSends2 sDAV m
Pulse(Auto-Mode).RefertoFigure42,Figure43and
Figure44.
AMC7823
SLAS453F –APRIL 2005–REVISED MARCH 2012
www.ti.com
ADC OPERATION (See AMC Status/Configuration Register and ADC Control Register)
(1) To avoid conflict, the data are not loaded into ADC-n data register from ADC-n temporary register until the data
transfer from the ADC-n data register to the shift register (if any) finishes.
(2) When the internal reference is selected, the bit GREF determines the input range: GREF = '0', 0 to 2.5V; GREF = '1',
0 to 5V (for 5V supply only). When an external reference is selected, the input range is 0 to 2 × V
REF
. The input
cannot be above AV
DD
.
Figure 41. ADC Structure
The ADC has nine analog inputs. Channels CH0 through CH7 receive external analog inputs. CH8 is dedicated
to the on-chip temperature sensor (see On-chip Temperature Sensor section).
ADC Trigger Signals (see AMC Status/Configuration Register)
The ADC can be triggered externally (external trigger mode) or internally (internal trigger mode). Bit ECNVT
(Enable CONVERT) of the AMC Status/Configuration Register determines which mode is used. When ECNVT is
set to '1', the ADC works in external trigger mode and the rising edge of the external signal CONVERT initiates
data conversion. When ECNVT is cleared to '0', the ADC is in internal trigger mode, and writing to the ADC
Control Register initiates conversion.
After the ADC is triggered, a group of analog inputs (up to nine channels may be specified) are multiplexed and
each channel is converted. The starting and ending addresses of the group of channels are specified by the bits
[SA3:SA0] and [EA3:EA0], respectively, in the ADC Control Register (see ADC Control Register for details). The
specified channels are converted sequentially from the starting to the ending address according to Table 12
(Analog Input Channel Address Map) and Table 13 (Analog Input Channel Range).
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