AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 ANALOG MONITORING AND CONTROL CIRCUIT Check for Samples: AMC7823 FEATURES APPLICATIONS • • • • • • 1 23 • • • • • • • • • • • 12-Bit ADC (200kSPS): – Eight Analog Inputs – Input Range 0 to 2 × VREF Programmable VREF, 1.25V or 2.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com DESCRIPTION (CONTINUED) The AMC7823 has an internal programmable reference (+2.5V or +1.25V), and an SPI serial interface. An external reference can be used as well. Typical power dissipation is 100mW. The analog input range is 0V to +5V, and the analog output range is 0V to +2.5V or 0V to +5V. The AMC7823 is ideal for multichannel applications where low power and small size are critical.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS: +5V At –40°C to +85°C, AVDD = 5V, DVDD = 5V, BVDD = 3V to 5V, using external 2.5V reference, unless otherwise noted.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS: +5V (continued) At –40°C to +85°C, AVDD = 5V, DVDD = 5V, BVDD = 3V to 5V, using external 2.5V reference, unless otherwise noted. AMC7823 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10 mA 100.0 100.5 μA PRECISION CURRENT SOURCE Output current range 0.01 Output current accuracy Iout = 100μA 99.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS: +5V (continued) At –40°C to +85°C, AVDD = 5V, DVDD = 5V, BVDD = 3V to 5V, using external 2.5V reference, unless otherwise noted. AMC7823 PARAMETER TEST CONDITIONS MIN TYP MAX 2.7 5 UNIT POWER-SUPPLY REQUIREMENTS Powersupply voltage AVDD DVDD (6) BVDD (7) Quiescent current of AVDD 5.5 V 2.7 5.5 V 2.7 5.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS: +3V At –40°C to +85°C, AVDD, DVDD, BVDD = 3V, using external 1.25V reference, unless otherwise noted. AMC7823 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC ANALOG INPUTS Input voltage range 0 2 × VREF V Input impedance 5 MΩ Input capacitance 15 pF Input leakage current ±1 μA ANALOG-TO-DIGITAL CONVERTER Resolution 12 No missing codes 12 Integral linearity Differential linearity Bits –1.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS: +3V (continued) At –40°C to +85°C, AVDD, DVDD, BVDD = 3V, using external 1.25V reference, unless otherwise noted. AMC7823 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10 mA 100.0 100.5 μA PRECISION CURRENT SOURCE Output current range 0.01 Output current accuracy Iout = 100μA 99.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 TERMINAL FUNCTIONS (continued) TERMINAL NO. DESCRIPTION NAME 11 CH0 Analog input channel 0 12 CH1 Analog input channel 1 13 CH2 Analog input channel 2 14 CH3 Analog input channel 3 15 AGND Analog ground 16 AVDD Analog power supply, +3V to +5V. Must be the same value as DVDD.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com TIMING CHARACTERISTICS: +5V At –40°C to +85°C, AVDD = DVDD = 5V, and BVDD = 5V, unless otherwise noted.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 tLag SS ttd tSCK twsck tf tLead tr SCLK twsck tsu thi Command BIT 15 (MSB) MOSI Don’t Care Command BIT 14 ...1 Command BIT 0 (LSB) Don’t Care READ COMMAND FROM THE HOST tA tv Hi−Z MISO tho DATA OUT BIT 15 (MSB) tdis DATA OUT BIT 14 DATA OUT BIT 13 ... 1 Hi−Z DATA OUT BIT 0 (LSB) MISO is in Hi-Z Before Finishing Address Decoding DATA READ FROM AMC7823 REGISTERS Note: If SS is High, MISO is in Hi-z Figure 1.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: ANALOG-TO-DIGITAL CONVERTER (ADC) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. INL (LSB) 1.0 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 DNL (LSB) 0 1.0 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 0 12 512 512 1024 1536 2048 2560 3072 3584 INL (LSB) DNL (LSB) 4096 0 512 1024 1536 2048 2560 3072 3584 Code Code Figure 3. Figure 4. LINEARITY ERROR vs CODE (+25°C, AVDD = 5V, VREF = 2.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: ANALOG-TO-DIGITAL CONVERTER (ADC) (continued) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. OFFSET ERROR AND OFFSET ERROR MATCH vs TEMPERATURE GAIN ERROR AND GAIN ERROR MATCH vs TEMPERATURE 4.0 AVDD = 5V VREF = 2.5V 0.8 0.6 0.4 Offset Error 0.2 Offset Error Match 0.0 −0.2 −0.4 −0.6 Delta Error from +25_ C (LSB) Delta Error from +25_C (LSB) 1.0 −0.8 2.0 −60 −40 −20 0 20 40 60 80 Gain Error 1.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: ANALOG-TO-DIGITAL CONVERTER (ADC) (continued) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. GAIN AND OFFSET ERROR vs 3V SUPPLY GAIN AND OFFSET ERROR MATCH vs 3V SUPPLY 12.0 1.0 VREF = 1.25V VREF = 1.25V 8.0 0.8 Error Match (LSB) Gain Error (LSB) 4.0 0 Offset −4.0 Gain Match 0.6 0.4 Offset Match 0.2 −8.0 −12.0 0 2.7 2.85 3.0 3.15 3.3 2.7 2.85 3.3 Figure 16.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: ANALOG-TO-DIGITAL CONVERTER (ADC) (continued) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. INTERNAL 2.5V REFERENCE (AVDD = 5V) INTERNAL 1.25V REFERENCE (AVDD = 2.7V) 25 60 50 Frequency (%) Frequency (%) 20 15 10 5 40 30 20 10 0 2.505 2.504 2.503 2.502 2.501 2.500 2.499 2.498 2.497 2.496 2.495 0 1.247 1.248 1.249 1.250 1.251 1.252 1.253 Histogram Bins (V) Histogram Bins (V) Figure 19.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: DIGITAL-TO-ANALOG CONVERTER (DAC) (continued) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. INL (LSB) 8.0 6.0 4.0 2.0 0 −2.0 −4.0 −6.0 −8.0 DNL (LSB) 0 1.0 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 512 0 1024 1536 2048 2560 3072 3584 INL (LSB) 8.0 6.0 4.0 2.0 0 −2.0 −4.0 −6.0 −8.0 DNL (LSB) 1.0 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1.0 0 4096 1536 2048 2560 3072 3584 4096 Figure 23.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: DIGITAL-TO-ANALOG CONVERTER (DAC) (continued) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. VOUT vs SOURCING AND SINKING CURRENT 6.0 3.0 5.0 2.5 4.0 Output Voltage (V) Sourcing Current 3.0 2.0 Sinking Current 1.0 AVDD = 5V VREF = 2.5V Gain = +2 2.0 Sourcing Current 1.5 1.0 Sinking Current AVDD = 2.7V VREF = 1.25V Gain = +2 0.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS: PRECISION CURRENT SOURCE At +25°C, AVDD = DVDD = 5V, unless otherwise noted. 100μA CURRENT SOURCE vs TEMPERATURE PRECISION_I_OUTPUT vs COMPLIANCE VOLTAGE 0.5 AVDD / VREF = 5V / 2.5V or 3V / 1.25V 0.3 Delta from Nominal (%) 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 −25 0 25 50 75 AVDD = 5V VREF = 2.5V 10µA (nom) 10mA (nom) 1mA (nom) 4.00 100 4.25 4.75 5.0 Figure 35.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS: PRECISION CURRENT SOURCE (continued) At +25°C, AVDD = DVDD = 5V, unless otherwise noted. CURRENT SOURCE PRODUCTION DISTRIBUTION (1.25V EXTERNAL REFERENCE) 70 60 Frequency (%) 50 40 30 20 10 100.5 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 0 Current (µA) Figure 38.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION DIGITAL INTERFACE The AMC7823 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. SPI slave devices, such as the AMC7823, depend on a master to start and synchronize transmissions.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 NOTE: If the ending address is equal to or smaller than the starting address, only the starting address is accessed. In this case, the operation applies only to the starting address; all remaining data and memory locations (if any) are ignored. In this manner, a single register may be addressed by setting [EADR4:EADR0] = 00000 or [SADR4:SADR0] ≥ [EADR4:EADR0]. Table 1.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com AMC7823 MEMORY MAP The AMC7823 has several 16-bit registers separated into two pages of memory, Page 0 and Page 1. The memory map is shown in Table 2. Locations that are marked Reserved read back 0x0000 if they are read by the host. Writing to these locations has no effect. Figure 40 explains the Read/Write operation. Table 2.
AMC7823 www.ti.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com ADC OPERATION (See AMC Status/Configuration Register and ADC Control Register) Out-of-Range Alarm of first four inputs being converted Out-of-Range ALARM Double-Buffered ADC Data Register To Shifter Register ADC−0 DATA ADC−0 TMPRY MUX CH0 External trigger works in Direct-Mode only. CH3 After conversion of CH-n finished, ADC-n TMPRY register is updated immediately. TMPRY register is a temporary register .
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 Conversion Mode When internal trigger mode is selected (ECNVT = '0'), two types of ADC conversion are available: direct-mode and auto-mode. The bit CMODE (Conversion MODE) of the ADC Control Register specifies the conversion mode. When external trigger mode is selected (ECNVT = '1'), only direct-mode conversion is available. In this case, bit CMODE in the ADC Control Register is ignored. (See Table 3.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com SS SS WRITE ADC CONTROL Register WRITE ADC Internal CONTROL Register 2nd Trigger 1st Internal Trigger WRITE ADC CONTROL Register MOSI Internal Trigger MOSI DAV 2ms DAV 1st Conversions, [SA3:SA0] to [EA3:EA0] 2nd Conversions, [SA3:SA0] to [EA3:EA0] 2nd Round of 1st Round of Conversions, Conversions, [SA3:SA0] to [EA3:EA0] [SA3:SA0] to [EA3:EA0] Figure 42. Internal Trigger, Direct-Mode Figure 43.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 The bit GREF in the AMC Status/Configuration Register selects between two preset internal reference values. When GREF = '0' (power-up default condition), the internal reference is set to 1.25V. When GREF = '1', the internal reference is 2.5V. GREF must be cleared to '0' when the power supply is less than 5V. When an external reference is applied, the input range is 0 to 2 × VREF, and is not affected by the bit GREF.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com ON-CHIP TEMPERATURE SENSOR The AMC7823 has an integrated temperature sensor to measure the on-chip temperature. This measurement relies on the characteristics of a semiconductor p-n junction operating at a known current level. The forward voltage of the diode (VBE) depends on the current passing through it and the junction temperature.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 DAC OPERATION (see DAC-n Data Registers and DAC Configuration Register) AMC7823 has eight double-buffered DACs. The outputs of the DACs can be updated synchronously or individually (asynchronously). Figure 47 illustrates the generic DAC structure.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com The DAC synchronous load signal can be the rising edge of the external signal ELDAC, or the internal signal ILDAC. Write BB00h into the Load DAC Register to generate ILDAC. When the DAC synchronous load signal occurs, all DACs with the bit SLDA-n set to '1' are updated simultaneously with the value of the corresponding DAC-n Data register. By setting the bit SLDA-n properly, several DACs can be updated at the same time.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 After power-on or reset, all DAC-n Data Registers and all DAC-n Latches are cleared to '0'. This clearing process results in all DAC outputs at 0V, gain of unity, and a full-scale output range preset to either 1.25V or equal to the external reference (if it is applied) because bits SREF and GREF are also cleared to '0'. Zero Code Output Value Each DAC buffer is clamped to prevent the output from going to 0V.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com REFERENCE The AMC7823 requires a reference voltage to drive the ADC, the DACs, and the precision current source. It can accommodate the application of an external reference voltage, or it can supply reference from an internal bandgap voltage circuit as shown in Figure 48. Pin 21, EXT_REF_IN, is common to either source. An internal 10kΩ resistor connects the internal reference source to pin 21.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 PRECISION CURRENT SOURCE The AMC7823 provides the user with a precision current source for driving an external component such as a thermistor. Output current from pin 5 is set by the value of the resistor (RSET) connected from pin 4 to the analog supply voltage. This resistor should be close to the AMC7823 to minimize any voltage drop from the analog supply to the resistor.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com Table 7. Precision Current Source Configuration (1) (2) SREF PTS PREFB GREF IO 0 0 Don't care Don't care 0 0 1 0 1 0 1 Don't care 0 0.5V/RSET (1) 0 1 1 1 0.5V/RSET (1) 1 0 Don't care Don't care 1 (2) 0 0 1 1 0 1 1 Don't care 0 (2) Equation 1 0 1 1 1 1 (2) Equation 1 VSET = 0.5V. Make GREF = 1 for 2.5V external reference; make GREF = 0 for 1.25V external reference.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 The ELDAC pin is an input pin for the external DAC synchronous load signal. The rising edge of ELDAC updates all DAC-n simultaneously that have the corresponding bit SLDA-n set to '1'. The AMC7823 has six GPIO pins, GPIO-n (n = 0, 1, 2, 3, 4, 5). Pins GPIO-4 and GPIO-5 are dedicated to general bidirectional digital I/O signals.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com Bit ALR-n of ALR Register Bit IOMOD-n in GPIO Register Bit IOST-n in GPIO Register GPIO-n ENABLE IOMOD-n = 0, ALR-n Pin IOMOD-n = 1, Digital I/O Pin Bit IOST-n (when reading) Figure 52.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 The value in the Threshold-Hi-n Register defines the upper bound threshold of the nth analog input, while the value in Threshold-Low-n defines the lower bound. These two bounds specify a window for the out-of-range detection. The out-of-range condition occurs when the input is set outside the window defined by these boundaries.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com REGISTERS This section describes each of the registers shown in the memory map of Table 2. The registers are named descriptively, according to their respective functions. NOTE: After power-on or reset, all ADC channels, all DACs, and the precision current source are in a powereddown state. The user must write the Power-Down Register properly in order to activate the desired components. For details, see the Power-Down Register section.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 When an external reference is used and SREF is set to '1', GREF has no impact on the reference. However, if SREF is cleared to '0', a 10kΩ resistor is connected between pin 21, EXT_REF_IN, and one of the two internal reference values dictated by the value of GREF. In this case, the external reference must be able to drive the 10kΩ load. The full-scale range of the ADC input is equal to 2 x VREF.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com DAC Configuration Register (Read/Write) Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 SLDA7 SLDA6 SLDA5 SLDA4 SLDA3 SLDA2 SLDA1 SLDA0 GDAC 7 SLDA-n Bit 6 GDAC 6 Bit 5 GDAC 5 Bit 4 GDAC 4 Bit 3 GDAC 3 Bit 2 GDAC 2 Bit 1 GDAC 1 Bit 0 LSB GDAC 0 DAC Synchronous Load Enable bit. SLDA-n = '1': Synchronous Load enabled.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 ADC Control Register (Read/Write; see ADC Operation and AMC Status/Configuration Register) This register specifies the ADC conversion mode and identifies the analog inputs to be converted. A write command to this register initiates conversion when the internal ADC trigger is selected (bit ECNVT = '0' in the AMC Status/Configuration Register).
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com Table 13. Analog Input Channel Range STARTING CHANNEL [SA3:SA0] ENDING CHANNEL [EA3:EA0] External trigger, direct mode Any one of CH0 to CH8 Any one from CH0 to CH8, but not less than [SA3:SA0] 0 Internal trigger, direct mode CH0 only. SA3:SA0 = '0000' Any one 1 Internal trigger, auto mode CH0 only.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 DAC-n Data Registers (n = 0, 1, 2, 3, 4, 5, 6, 7) (see the DAC Operation section) This register is the input Data Register for DAC-n that buffers the DAC-n Latch Register. The DAC-n output is updated only when Latch is loaded. Under an asynchronous load (bit SLDA-n = '0' in the DAC Configuration Register), the value of the DAC-n Data Register is transferred into the Latch immediately after Data Register is written.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com ALR Register (see Figure 53) Bit 15 MSB X Bit 14 X Bit 13 X Bit 12 X Bit 11 ALR-3 Bit 10 ALR-2 Bit 9 ALR-1 Bit 8 ALR-0 Bit 7 X Bit 6 X Bit 5 X Bit 4 X Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 LSB 0 X : Don't Care The first four analog inputs in the group defined by bits [SA3:SA0] and [EA3:EA0] in the ADC Control Register are implemented with out-of-range detection. [Bit 3:Bit 0] Must be '0' to ensure correct operation of alarm detection.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 To avoid loss of alarm information in bits IOST-n during power-down of the ADC, change to direct conversion mode (see ADC Control Register) before power-down and do not issue a convert command while the ADC is powered down. NOTE: When GPIO-n works as a general-purpose I/O pin, bit IOST-n does not change during the power-down procedure. After power-on or reset, all bits in the GPIO Register are set to '1'.
AMC7823 SLAS453F – APRIL 2005 – REVISED MARCH 2012 www.ti.com POWER-DOWN REGISTER (Read/Write) NOTE: After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled by this register are in the powered-down or Off state. To avoid loss of alarm data during power-down of the ADC, change the ADC conversion to direct mode (see ADC Control Register) before power-down and do not issue a convert command while the ADC is powered down.
AMC7823 www.ti.com SLAS453F – APRIL 2005 – REVISED MARCH 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January 2010) to Revision F Page • Changed Level of Pin GALR and DAV, IOH = 0.7mA parameter minimum and maximum specifications in +5V Electrical Characteristics table .............................................................................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Mar-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AMC7823IRTAR WQFN RTA 40 2000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 AMC7823IRTAT WQFN RTA 40 250 330.0 16.4 6.3 6.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 29-Mar-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AMC7823IRTAR WQFN RTA 40 2000 336.6 336.6 28.6 AMC7823IRTAT WQFN RTA 40 250 336.6 336.6 28.
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