Datasheet

AMC7812
www.ti.com SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
PIN DESCRIPTIONS (continued)
PIN (QFN / HTQFP)
DESCRIPTION
NO. NAME
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter
a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.
17 DAC-CLR-0 However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC
Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,
regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.
18 DAC5-OUT
19 DAC4-OUT Output of DAC channels 3, 4, and 5
20 DAC3-OUT
21 AGND4
Analog ground
22 AGND3
Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, DAC5-OUT, must be
23 AV
CC2
tied to AV
CC1
24 DAC2-OUT
25 DAC1-OUT Output of DAC channels 0, 1, and 2
26 DAC0-OUT
27 D2–/GPIO-6 Remote sensor D2 negative input when D2 enabled; GPIO-6 when D2 disabled. Pull-up required for output.
28 D2+/GPIO-7 Remote sensor D2 positive input when D2 enabled; GPIO-7 when D2 disabled. Pull-up required for output.
29 D1–/GPIO4 Remote sensor D1 negative input when D1 enabled; GPIO-6 when D1 disabled. Pull-up required for output.
30 D1+/GPIO-5 Remote sensor D1 positive input when D1 enabled; GPIO-7 when D1 disabled. Pull-up required for output.
External ADC reference input when external V
REF
is used to drive ADC. Compensation capacitor connection
31 ADC-REF-IN/CMP
(connect 4.7µF capacitor between this pin and AGND) when Internal V
REF
is used to drive ADC.
32 ADC-GND ADC ground. Must be connected to AGND.
33- Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be
CH0 to CH15
48 programmed as differential or single-ended.
49 AV
DD1
Positive analog power supply
50 AV
DD2
51 DAC6-OUT
52 DAC7-OUT Output of DAC channels 6, 7, and 8
53 DAC8-OUT
54 AGND1
Analog ground
55 AGND2
Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, DAC11-OUT, must
56 AV
CC1
be tied to AV
CC2
57 REF-OUT Internal reference output
58 REF-DAC DAC reference Input
59 DAC9-OUT
60 DAC10-OUT Output of DAC channels 9, 10, and 11
61 DAC11-OUT
Global alarm. Open drain output. External 10kΩ pull-up resistor required. This pin goes low (active) when one
62 ALARM
(or more) of the analog channels are out of range.
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter
a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.
63 DAC-CLR-1 However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC
Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,
regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.
64 DGND2 Digital ground
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