Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RESET
DAV
CNVT
CS
SDI/SDA
SCLK/SCL
DGND
IOV
DV
/A0
SDO/A1
A2
SPI/I2C
GPIO-0
GPIO-1
GPIO-2
GPIO-3
DD
DD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DAC-CLR-0
DAC5-OUT
DAC4-OUT
DAC3-OUT
AGND4
AGND3
AV
DAC2-OUT
DAC1-OUT
DAC0-OUT
D2-/GPIO-6
D2+/GPIO-7
D1-/GPIO-4
D1+/GPIO-5
ADC-REF-IN/CMP
ADC-GND
CC2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DGND2
DAC11-OUT
DAC10-OUT
DAC9-OUT
REF-DAC
REF-OUT
AV
AGND2
AGND1
DAC8-OUT
DAC7-OUT
DAC6-OUT
AV
AV
DAC-CLR-1
ALARM
CC1
DD2
DD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RESET
DAV
CNVT
CS
SDI/SDA
SCLK/SCL
DGND
IOV
DV
/A0
SDO/A1
A2
SPI/I2C
GPIO-0
GPIO-1
GPIO-2
GPIO-3
DD
DD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DAC-CLR-0
DAC5-OUT
DAC4-OUT
DAC3-OUT
AGND4
AGND3
AV
DAC2-OUT
DAC1-OUT
DAC0-OUT
D2 /GPIO-6
D2+/GPIO-7
D1 /GPIO-4
D1+/GPIO-5
ADC-REF-IN/CMP
ADC-GND
CC2
-
-
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DGND2
DAC11-OUT
DAC10-OUT
DAC9-OUT
REF-DAC
REF-OUT
AV
AGND2
AGND1
DAC8-OUT
DAC7-OUT
DAC6-OUT
AV
AV
DAC-CLR-1
ALARM
CC1
DD2
DD1
AMC7812
SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
www.ti.com
PIN CONFIGURATION
RGC PACKAGE
PAP PACKAGE
QFN-64
HTQFP-64
(TOP VIEW)
(TOP VIEW)
PIN DESCRIPTIONS
PIN (QFN / HTQFP)
DESCRIPTION
NO. NAME
1 RESET Reset input, active low. Logic low on this pin causes the device to perform a hardware reset.
Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion
2 DAV ends. In auto mode, a 1µs pulse (active low) appears on this pin when a conversion cycle finishes (see the
Primary ADC Operation and Registers sections for details). DAV stays high when deactivated.
3 CNVT External conversion trigger, active low. The falling edge starts the sampling and conversion of the ADC.
Serial interface data. SDI for the serial peripheral interface (SPI) when the SPI/I2C pin is high. SDA for I
2
C
4 SDI/SDA
when the SPI/I2C pin is low.
Serial clock input of the main serial interface. SPI clock when the SPI/I2C pin is high; I
2
C clock when the
5 SCLK/SCL
SPI/I2C pin is low.
6 DGND Digital ground
7 IOV
DD
Interface power supply
8 DV
DD
Digital power supply (+3V to +5V). Must be the same value as AV
DD
.
Chip select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I
2
C when the SPI/I2C
9 CS/A0
pin is low.
10 SDO/A1 SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I
2
C when the SPI/I2C pin is low.
11 A2 Slave address selection A2 for I
2
C when the SPI/I2C pin is low.
Interface selection pin. Digital input. When this pin is tied to IOV
DD
, the SPI is enabled and the I
2
C interface is
12 SPI/I2C
disabled. When this pin is tied to ground, the SPI is disabled and the I
2
C interface is enabled.
13 GPIO-0
14 GPIO-1
General-purpose digital input/output. This pin is a bidirectional open-drain, digital input/output, and requires an
external pull-up resistor. See the General Purpose Input/Output Pins section for more details.
15 GPIO-2
16 GPIO-3
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