Datasheet

AMC7812
SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013 www.ti.com
ADC CHANNEL REGISTER 1 (Read/Write, Address = 51h, Default = 0000h)
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 SE13 SE14 SE15 0 0 0 0 0 0 0 0 0 0 0 0
These bits specify the external analog auxiliary input channels (CH13, CH14,and CH 15) to be converted. The
specified channel is accessed sequentially in the order from bit 14 to bit 0 of ADC Channel Register 0, and then
bit 14 to bit 12 of ADC Channel Register 1. The input is converted when the corresponding bit is set ('1').
Bits[14:12] SEn: External single-ended analog input CHn. The result is stored in the ADC-n-Data Register in straight binary format.
ADC GAIN REGISTER (Read/Write, Address = 52h, Default = FFFFh)
MSB
BIT BIT BIT BIT BIT BIT LSB
15 14 13 12 11 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADG0 ADG1 ADG2 ADG3 ADG4 ADG5 ADG6 ADG7 ADG8 ADG9 ADG10 ADG11 ADG12 ADG13 ADG14 ADG15
Bit 15 ADG0.
When ADG0 = '1', the analog input range of single-ended input CH0 (SE0) is 0 to (2 · V
REF
) or differential input pair
DF(CH0+/CH1–) is (–2 · V
REF
) to (+2 · V
REF
).
When ADG0 = '0', the analog input range of single-ended input CH0 (SE0) is 0 to V
REF
or differential input pair
DF(CH0+/CH1–) is –V
REF
to +V
REF
.
Bit 14 ADG1.
When ADG1 = '1', the analog input range is 0 to (2 · V
REF
).
When ADG1 = '0', the analog input range of single-ended input CH1 (SE1) is 0 to V
REF
.
Bit 13 ADG2.
When ADG2 = '1', the analog input range of single-ended input CH2 (SE2) is 0 to (2 · V
REF
) or differential input pair
DF(CH2+/CH3–) is (–2 · V
REF
) to (+2 · V
REF
).
When ADG2 = '0', the analog input range of single-ended input CH2 (SE2) is 0 to V
REF
or differential input pair
DF(CH2+/CH3–) is –V
REF
to +V
REF
.
Bit 12 ADG3.
When ADG3 = '1', the analog input range is 0 to (2 · V
REF
).
When ADG3 = '0', the analog input range of single-end input CH3 (SE3) is 0 to V
REF
.
Bit[11:0] ADG4 to ADG15.
When these bits = '1', the analog input range is 0 to (2 · V
REF
).
When these bits = '0', the analog input range of CHn (where n = 4 to 15) is 0 to V
REF
AUTO-DAC-CLR-SOURCE REGISTER (Read/Write, Address = 53h, Default = 0004h)
This register selects which alarm forces the DAC into a clear state, regardless of which DAC operation mode is
active, auto or manual.
Table 26. AUTO-DAC-CLR-SOURCE Register
BIT NAME DEFAULT R/W DESCRIPTION
15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
CH0 alarm clear bit.
If CH0-ALR_CLR = '1', and if both the ACLRn bit in the AUTO-DAC-CLR-EN Register and
14 CH0-ALR-CLR 0 R/W the CH0-ALR bit in the Status Register are set ('1'), then DAC-n is forced to a clear status.
If CH0-ALR_CLR = '0', then CH1-ALR goes to '1' and does not force any DAC to a clear
status.
CH1 alarm clear bit.
If CH1-ALR_CLR = '1', and if both the ACLRn bit in the AUTO-DAC-CLR-EN Register and
13 CH1-ALR-CLR 0 R/W the CH1-ALR bit in the Status Register are set ('1'), then DACn is forced to a clear status.
If CH1-ALR_CLR = '0', then CH1-ALR goes to '1' and does not force any DAC to a clear
status.
CH2 alarm clear bit.
If CH2-ALR_CLR = '1', and if both the ACLRn bit in the AUTO-DAC-CLR-EN Register and
12 CH2-ALR-CLR 0 R/W the CH2-ALR bit in the Status Register are set ('1'), then DACn is forced to a clear status.
If CH2-ALR_CLR = '0', then CH2-ALR goes to '1' and does not force any DAC to a clear
status.
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