Datasheet

AMC7812
SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013 www.ti.com
AMC CONFIGURATION REGISTER 0 (Read/Write, Address = 4Ch, Default = 2000h)
Table 16. AMC Configuration Register 0
BIT NAME DEFAULT R/W DESCRIPTION
15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC Conversion Mode Bit. This bit selects between the two operating conversion modes
(direct or auto).
CMODE = '0': Direct mode. The analog inputs specified in the ADC Channel Registers are
converted sequentially (see the ADC Channel Registers) one time. When one set of
13 CMODE 1 R/W conversions is complete, the ADC is idle and waits for a new trigger.
CMODE = '1': Auto mode. The analog inputs specified in the AMC Channel Registers are
converted sequentially and repeatedly (see the ADC Channel Registers). When one set of
conversions is complete, the ADC multiplexer returns to the first channel and repeats the
process. Repetitive conversions continue until the CMODE bit is cleared ('0').
Internal conversion bit.
12 ICONV 0 R/W Set this bit to '1' to start the ADC conversion internally. The bit is automatically cleared ('0')
after the ADC conversion starts.
Load DAC bit. Set this bit to '1' to synchronously load the DAC Data Registers, which are
programmed for synchronous update mode (SLDAC-n = 1). The AMC7812 updates the
DAC Latch only if the ILDAC bit is set ('1'), thereby eliminating any unnecessary glitch. Any
11 ILDAC 0 R/W
DAC channels that have not been accessed are not reloaded. When the DAC Latch is
updated, the corresponding output changes to the new level immediately. This bit is
cleared ('0') after the DAC Data Register is updated.
ADC V
REF
select bit.
When this bit = '0', the internal reference buffer is off, and the external reference drives the
10 ADC-REF-INT 0 R/W ADC.
When this bit = '1', the internal buffer is on and the internal reference drives the ADC. Note
that a compensation capacitor is required.
Enable ALARM pin bit.
9 EN-ALARM 0 R/W When this bit = '0', the ALARM pin is disabled.
When this bit = '1', the ALARM pin is enabled.
8 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC Data available flag bit. For Direct mode only. Always cleared (set to '0') in Auto mode.
DAVF = '1': The ADC conversions are complete and new data are available.
DAVF = '0': The ADC conversion is in progress (data are not ready) or the ADC is in Auto
mode.
In Direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF = '1', and goes
7 DAVF R high when DAVF = '0'.
In Auto mode, DAVF is always cleared to '0'. However, a 1µs pulse (active low) appears on
the DAV pin when the last input specified in the ADC Channel Registers is converted.
DAVF is cleared to '0' in one of three ways: (1) reading the ADC Data Register, (2) starting
a new ADC conversion, or (3) writing '0' to this bit. Reading the Status Register does not
clear this bit.
Global alarm bit. This bit is the OR function of all individual alarm bits of the Status
6 GALR 0 R Register. This bit is set ('1') when any alarm condition occurs, and remains '1' until the
Status Register is read. This bit is cleared ('0') after reading the Status Register.
5 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
4 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
3 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
2 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
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