Datasheet

AMC7812
SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013 www.ti.com
ADC-n-DATA REGISTERS (Read-Only, Addresses = 23h to 32h)
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Bits[11:0] ADC data.
Four ADC data registers are available. The ADC-n-Data Registers (where n = 0 to 15) store the conversion
results of the corresponding analog channel-n, as shown in Table 15.
Table 15. ADC Data Register Definitions
CONVERSION RESULT
INPUT CHANNEL INPUT TYPE STORED IN FORMAT
Channel 0 Single-Ended ADC-0-Data Register Straight binary
Channel 1 Single-Ended ADC-1-Data Register Straight binary
Channel 2 Single-Ended ADC-2-Data Register Straight binary
Channel 3 Single-Ended ADC-3-Data Register Straight binary
CH0+/CH1– Differential ADC-0-Data Register Twos complement
CH2+/CH3– Differential ADC-2-Data Register Twos complement
Channel 4 Single-Ended ADC-4-Data Register Straight binary
Channel 5 Single-Ended ADC-5-Data Register Straight binary
Channel 6 Single-Ended ADC-6-Data Register Straight binary
Channel 7 Single-Ended ADC-7-Data Register Straight binary
Channel 8 Single-Ended ADC-8-Data Register Straight binary
Channel 9 Single-Ended ADC-9-Data Register Straight binary
Channel 10 Single-Ended ADC-10-Data Register Straight binary
Channel 11 Single-Ended ADC-11-Data Register Straight binary
Channel 12 Single-Ended ADC-12-Data Register Straight binary
Channel 13 Single-Ended ADC-13-Data Register Straight binary
Channel 14 Single-Ended ADC-14-Data Register Straight binary
Channel 15 Single-Ended ADC-15-Data Register Straight binary
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