Datasheet
AMC7812
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SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
TEMPERATURE DATA REGISTERS (Read-Only)
In twos complement format, 0.125°C/LSB.
LT-Temperature-Data Register (Address = 00h, Default 0000h, 0°C)
Store the local temperature sensor reading in twos complement data format.
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LT-11 LT-10 LT-9 LT-8 LT-7 LT-6 LT-5 LT-4 LT-3 LT-2 LT-1 LT-0 0 0 0 0
D1-Temperature-Data Register (Address = 01h, Default 0000h, 0°C)
Store the remote temperature sensor D1 reading in twos complement data format.
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
D1-11 D1-10 D1-9 D1-8 D1-7 D1-6 D1-5 D1-4 D1-3 D1-2 D1-1 D1-0 0 0 0 0
D2-Temperature-Data Register (Address = 02h, Default 0000h, 0°C)
Store the remote temperature sensor D2 reading in twos complement data format.
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
D2-11 D2-10 D2-9 D2-8 D2-7 D2-6 D2-5 D2-4 D2-3 D2-2 D2-1 D2-0 0 0 0 0
TEMPERATURE CONFIGURATION REGISTER (Read/Write, Address = 0Ah)
When using the SPI, the following bit configuration must be used; default = 003Ch.
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 0 0 0 0 0 0 D2EN D1EN LTEN RC 0 0
When using the I
2
C interface, the following bit configuration must be used; default = 3CFFh.
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 D2EN D1EN LTEN RC 0 0 1 1 1 1 1 1 1 1
The bit descriptions are shown in Table 11.
Table 11. Temperature Configuration Register Bit Descriptions
NAME DEFAULT R/W DESCRIPTION
Remote temperature sensor D2 enable.
D2EN 1 R/W If this bit = '1', D2 is enabled.
If this bit = '0', D2 is disabled.
Remote temperature sensor D1 enable.
D1EN 1 R/W If this bit = '1', D1 is enabled.
If this bit = '0', D1 is disabled.
Local temperature sensor enable.
LTEN 1 R/W If this bit = '1', LT is enabled.
If this bit = '0', LT is disabled.
Resistance correction enable.
RC 1 R/W If this bit = '1', correction is enabled.
If this bit = '0', correction is disabled.
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