Datasheet

SDI
SDO
CS
R0
R1 R2
R3
XX
D0
D1 D2
D3
AnyCommand
R
XX=Don’tcare,undefined
n N
n N
=ReadCommandforRegister
D =DatafromRegister
SDI
SDO
W0
W1 W2
W3
XX
CS
XX XX XX
W =WriteCommandforRegister
XX=Don’tcare,undefined
n N
CS SCLK SDI SDO
AMC7812
www.ti.com SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
Standalone Operation
In standalone mode, as shown in Figure 105, each AMC7812 has its own SPI bus. The serial clock can be
continuous or gated. The first falling edge of CS starts the operation cycle. Exactly 24 falling clock edges must be
applied before CS is brought high again. If CS is brought high before the 24th falling SCLK edge, or if more than
24 falling SCLK edges are applied before CS is brought high, then the input data are incorrect. The device input
register is updated from the Shift Register on the rising edge of CS, and data are automatically transferred to the
addressed registers as well. In order for another serial transfer to occur, CS must be brought low again.
Figure 106 and Figure 107 show write, and read operations in standalone mode.
Figure 105. Standalone Operation
Figure 106. Write Operation in Standalone Mode
Figure 107. Read Operation in Standalone Mode
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