Datasheet

AMC7812
www.ti.com SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
DAC Output
The output range is programmable from 0 to (2 · V
REF
) or from 0 to (5 · V
REF
), depending on the gain bits in the
DAC Gain Register. The maximum output is AV
CC
. The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0V to AV
CC
. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics. The slew rate is 1.5V/μs with a typical ¼ to ¾ scale settling
time of 3μs with the output unloaded.
Double-Buffered DAC Data Registers
There are 12 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC Data
Register. Data are initially written to an individual DAC-n-Data Register and then transferred to the corresponding
DAC-n Latch. When the DAC-n Latch is updated, the output of DAC-n changes to the newly set value. When the
host reads the register memory map location labeled DAC-n Data, the value held in the DAC-n Latch is returned
(not the value held in the input DAC-n-Data Register).
Full-Scale Output Range
The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain
of the DAC output buffer (V
REF
· Gain). The gain bits of the DAC Gain Register set the output range of the
individual DAC-n. The full-scale output range of each DAC is limited by the analog power supply. The maximum
output from the DAC must not be greater than AV
CC
, and the minimum output must not be less than AGND.
DAC Output After Power-On Reset
After power on, the DAC output buffer is in power-down mode. The output buffer is in a Hi-Z state and the DAC-
Out output pin connects to the analog ground through an internal 10kΩ resistor. After power on or hardware
reset, all DAC-n-Data Registers, all DAC-n Latches, and the DAC output are set to default values (000h).
Load DAC Latch
See Figure 91 for the structure of the DAC register and DAC latch. The contents of the DAC-n Latch determine
the output level of the DAC-n pin. After writing to the DAC-n-Data Register, the DAC Latch can be loaded in the
following ways:
• In asynchronous mode (SLDAC-n bit = '0'), the data are loaded into the DAC-n Latch immediately after the
write operation.
• In synchronous mode (SLDAC-n bit = '1'), the DAC latch updates when the synchronous DAC loading signal
occurs. Setting the ILDAC bit in AMC Configuration Register 0 generates the loading signal.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Links: AMC7812