Datasheet

CNVT
DAV
FirstConversionof
theChannelsSpecifiedin
theADCChannelRegister
First
Trigger
b)ExternalTrigger,AutoMode:
1 sm
CNVT
DAV
SecondConversionof
theChannelsSpecifiedin
theADCChannelRegister
ThirdConversionof
theChannelsSpecifiedin
theADCChannelRegister
First
Trigger
Second
Trigger
Third
Trigger
FirstConversionof
theChannelsSpecifiedin
theADCChannelRegister
SecondConversionof
theChannelsSpecifiedin
theADCChannelRegister
ThirdConversionof
theChannelsSpecifiedin
theADCChannelRegister
a)ExternalTrigger,DirectMode:
SS
SDI
DAV
SetICONV
bitto ‘1’
DATA
First
Internal
Trigger
ReadData
DATA
ReadData
SetICONV
bitto ‘1’
Second
Internal
Trigger
FirstConversionof
theChannelsSpecifiedin
theADCChannelRegister
SecondConversionof
theChannelsSpecifiedin
theADCChannelRegister
SS
SDI
DAV
SetICONV
bitto ‘1’
Internal
Trigger
1 sm
FirstConversionof
theChannelsSpecifiedin
theADCChannelRegister
SecondConversion ThirdConversion
b)InternalTrigger,AutoMode:
a)InternalTrigger,DirectMode:
AMC7812
www.ti.com SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
Handshaking with the Host (see AMC Configuration Register 0)
The DAV pin and the DAVF (data available flag) bit in AMC Configuration Register 0 provide handshaking with
the host. Pin and bit status depend on the conversion mode (direct or auto), as shown in Figure 84 and
Figure 85. In direct mode, after ADC-n-Data Registers of all of the selected channels are updated, the DAVF bit
in AMC Configuration Register 0 is set immediately to '1', and the DAV pin is active (low) to signify that new data
are available. Reading the ADC-n-Data Register or restarting via the external CNVT pin, the ADC clears the
DAVF bit to '0' and deactivates the DAV pin (high). If an internal convert start (ICONV bit) is used to start the new
ADC conversion, in order to reset the DAV status, an ADC-n-Data Register must be read after the current
conversion finishes before a new conversion can be started.
In auto-mode, after the ADC-n-Data Registers of the selected channels are updated, a pulse of 1µs (low)
appears on the DAV pin to signify that new data are available. However, the DAVF bit is always cleared to '0' in
auto-mode.
Figure 84. ADC Internal Trigger
Figure 85. ADC External Trigger
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