Datasheet

SDA
Sr
Sr
t
FDA
t
RDA
t
SU, STA
t
HD, STA
P
SCL
t
HD, DAT
t
SU, DAT
t
RCL1
(1)
t
RCL1
(1)
t
HIGH
t
LOW
t
LOW
t
RCL
t
FCL
t
HIGH
t
SU, STO
=CurrentSourcePull-Up
=ResistorPull-Up
Sr=RepeatedSTARTCondition
P=STOPCondition
AMC7812
www.ti.com SBAS513E –JANUARY 2011–REVISED SEPTEMBER 2013
(1) First rising edge of the SCL signal after Sr and after each acknowledge bit.
Figure 2. Timing for High-Speed (Hs) Mode Devices on the I
2
C Bus
TIMING CHARACTERISTICS: SDA and SCL for Hs Mode
(1)
At –40°C to +105°C, AV
DD
= 4.5V to 5.5V, DV
DD
= 2.7V to 5.5V, AGND = DGND = 0V, and IOV
DD
= 2.7V to 5.5V, unless
otherwise noted.
C
B
= 10pF to 100pF C
B
= 400pF
PARAMETER MIN MAX MIN MAX UNIT
f
SCL
(2)
SCL clock frequency 0 3.4 0 1.7 MHz
t
SU, STA
Setup time for (repeated) start condition 160 — 160 — ns
t
HD, STA
Hold time (repeated) start condition 160 — 160 — ns
t
LOW
Low period of the SCL clock 160 — 320 — ns
t
HIGH
High period of the SCL clock 60 — 120 — ns
t
SU, DAT
Data setup time 10 — 10 — ns
t
HD, DAT
Data hold time 0 70 0 150 ns
t
RCL
Rise time of SCL signal 10 40 20 80 ns
Rise time of SCL signal after a repeated start condition
t
RCL1
10 80 20 160 ns
and after an acknowledge bit
t
FCL
Fall time of SCL signal 10 40 20 80 ns
t
RDA
Rise time of SDA signal 10 80 20 160 ns
t
FDA
Fall time of SDA signal 10 80 20 160 ns
t
SU, STO
Set-up time for stop condition 160 — 160 — ns
C
B
(3)
Capacitive load for SDA and SCL lines 10 100 — 400 pF
t
SP
Pulse width of spike suppressed 0 10 0 10 ns
(1) All values refer to V
IHmin
and V
ILmax
levels.
(2) An SCL operating frequency of at least 1kHz is recommended to avoid activating the I
2
C timeout function. See the Timeout Function
section for details.
(3) For bus line loads where C
B
is between 100pF and 400pF, the timing parameters must be linearly interpolated.
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