Datasheet

PARALLEL MODE 2
TIMING CHARACTERISTICS
(1)
ADDR
ADDR
ADDR+1
MSB LSB MSB
t
w1
t
w2
t
d1
t
w3
t
w4
t
w5
t
d4
t
d3
t
d2
AD(7:0)
Internaladdress
Parallelmode2,writeaccess
CS
WR
RD
ALE
t
su1
t
h1
t
su2
t
h2
ADDR
MSB
LSB MSB
ADDR ADDR+1
t
d5
t
d6
t
w6
t
w7
t
d9
AD(7:0)
Internaladdress
Parallelmode2,readaccess
CS
WR
RD
ALE
t
d7
t
d8
AMC1210
www.ti.com .............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009
Over recommended operating free-air temperature range at – 40 ° C to +125 ° C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted.
PARAMETER
(2)
MIN MAX UNIT
t
w1
CS low width 40 ns
t
w2
CS high width 5 ns
t
d1
Delay time from ALE low to CS high 5 ns
t
d2
Delay time from WR high to CS high 5 ns
t
d3
Delay time from CS low to WR low 3 ns
t
w3
WR low width 10 ns
t
w4
WR high width 10 ns
t
w5
ALE high width 10 ns
t
d4
Delay time from ALE low to WR low 10 ns
t
su1
Setup time from address valid to ALE low 6 ns
t
h1
Hold time from ALE low to address invalid 5 ns
t
d5
Delay time from CS low to RD low 0 ns
t
su2
Setup time from data valid to WR high 6 ns
t
h2
Hold time from WR high to data invalid 5 ns
t
d6
Delay time from RD high to CS high 6 ns
t
w6
RD low width 30 ns
t
w7
RD high width 13 ns
t
d7
Delay time from RD low to data valid 30 ns
t
d8
Delay time from RD high to databus in tristate 0 10 ns
t
d9
Delay time from ALE low to RD low 10 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) t
w2
is obsolete if CS stays low between the WR, RD and ALE pulses.
Figure 5. Parallel Mode 2 Timing
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