Datasheet

SPI INTERFACE MODES
TIMING CHARACTERISTICS
(1)
t
c1
t
w1
Commandbit
R/W
Address
A4
Address
A0(LSB)
Address
A6(MSB)
DataIN
D15(MSB)
D14
DataIN
D0(LSB)
t
d2
t
d1
t
h1
t
su1
1 2 4 8 9 10 24
DataOUT
D15(MSB)
D14
DataOUT
D0(LSB)
t
d4
t
w2
t
d3
AD0
3
Address
A5
CS
t
d5
WR
RD
t
c1
t
w1
Commandbit
R/W
Address
A4
Address
A0(LSB)
Address
A6(MSB)
DataIN
D15(MSB)
D14
DataIN
D0(LSB)
t
d2
t
d1
t
h1
t
su1
1 2
4 8 9 10
24
DataOUT
D15(MSB)
D14
DataOUT
D0(LSB)
t
d5
t
d4
t
w2
t
d3
3
Address
A5
25
AD0
CS
WR
RD
AMC1210
www.ti.com .............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009
Over recommended operating free-air temperature range at – 40 ° C to +125 ° C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted.
Option 1 Option 2
PARAMETER MIN MAX MIN MAX UNIT
t
c1
WR period 40 25 ns
t
w1
WR HIGH or LOW time 10 10 ns
t
d1
Delay time from CS falling to WR rising edge 0 0 ns
t
d2
Delay time from CS falling to ADO not tristate 10 10 ns
t
su1
Data setup time 5 5 ns
t
h1
Input data hold time 5 5 ns
t
d3
Output data delay time 24 24 ns
t
d4
Enable lag time 10 10 ns
t
d5
ADO disable time 10 10 ns
t
w2
Sequential transfer delay 15 15 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Figure 2. SPI Interface Option 1 — SPI Normal Interface
Figure 3. SPI Interface Option 2 — SPI Fast Interface ( > 25MHz)
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