Datasheet

Mode 1 (TM = 1)
SH1
or
SH2
TIMER
TIME
REGISTER
CLKx
2 31 61 63 6462 65 66 67 125 127 128126 1 2 3
PreviousValue 128
61 63 6462 65 66 67 68 70 7169
MODE1(TM=1)
Mode 2 (TM = 0)
ACK
TIMER
TIME
REGISTER
MODE2(TM=0)
CLKx
2 31 1 3
...
2
... ... ...
125 127 128
129
126 1
PreviousValue
128
2 63 643 65 66 67
67
68 70 7169
SH1
or
SH2
DATA
REGISTER
DataValid
AMC1210
www.ti.com .............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009
In Mode 1, the time measure unit updates the Time Register with the elapsed amount of incoming modulator
clock cycles between two rising edges of the selected sample-and-hold signal (selected by the SHS bit of the
Control Parameter Register ). This mode can be used to measure the speed of the modulator clock or determine
the number of input bits that have been clocked into the filter module. Each time a positive edge of the selected
sample-and-hold is detected, the Time Register will be updated with the time counter value, and the time counter
will be reset. Figure 18 shows an example of a typical functional timer sequences in Mode 1.
Figure 18. Typical Functional Timer Sequence, Mode 1 (TM = 1)
In Mode 2, the time measure unit updates the Time Register with the elapsed amount of system clock cycles
from the last available data to the next rising edge of the selected sample-and-hold signal. Each time data is
available, that is, when the sinc filter or the integrator has new data, the timer will reset. The timer continuously
counts when a rising edge of the selected sample-and-hold signal occurs. At this point, the Time Register is
updated with the time counter value, and the time counter will be reset. Figure 19 shows an example of a typical
functional timer sequence in Mode 2.
Since the Time Register is a 16-bit register, the maximum time measured is 65,536 clock cycles. The bit TOx in
the Status Register is set to high when the time counter receives an overflow (that is, when the counter changes
from 0xFFFF to 0x0000). This status bit is reset when the Status Register is read.
Figure 19. Typical Functional Timer Sequence, Mode 2 (TM = 0)
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