Datasheet

Integrator Unit
Sample-and-Hold Mode (IMOD = 1)
Oversampling Mode (IMOD = 0)
Integrator Overflow
AMC1210
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The integrator allows digital integration (summation) of the filter output data or the direct modulator input data
when the sinc filter unit is bypassed. It consists of a parameterized integrator and a data shift unit. The integrator
is a simple 32-bit binary two's complement accumulator. The time of integration is determined by either the IOSR
value or an external sample-and-hold signal. The bit IMOD in the Integrator Parameter Register determines
which mode is used.
The integrator is enabled by setting the bit IEN in the Integrator Parameter Register to high. When IEN is low, the
integrator is disabled, reset, and bypassed.
The input to the integrator is fed by the sinc filter unit. This can be adjusted to allow the input to feed directly into
the integrator. See Bypassing the Sinc Filter Unit .
If Sample-and-Hold Mode is selected, the SHS bit in the Control Parameter Register determines which
sample-and-hold signal is used to determine the total integration time. When a rising edge occurs on the selected
sample-and-hold pin, the resulting integrator value is stored in the Data Register and the integrator is reset.
In Oversampling Mode, the integrator sums a preset number of samples from the sinc filter unit, determined by
an oversampling ratio value (IOSR) in the Integrator Parameter Register . The integrator can be configured with
oversampling ratios continuously between 1 and 128. The integrator is sampled at the data output rate of the
sinc filter unit. Table 11 shows the different full-scale values that the integrator can store with different
oversampling ratios, assuming that the sinc filter unit is set to SOSR = 256 at the full-scale output.
Table 11. Peak Data Values
for Different IOSR Values
INTEGRATOR OUTPUT MAX
IOSR (with a Sinc
3
Structure)
x – (SOSR
3
)(x) to (SOSR
3
)(x)
4 – 67,108,864 to 67,108,856
8 – 134,217,728 to 134,217,712
16 – 268,435,456 to 268,435,424
32 – 536,870,912 to 536,870,848
64 – 1,073,741,824 to 1,073,741,696
128 – 2,147,483,648 to 2,147,483,648
The start of an integrator cycle in Oversampling Mode is controlled by the sinc filter unit. A new integrator cycle is
started when the sinc filter is enabled. The bit MFE in the Clock Divider Register can be used to synchronize the
integrator unit in all four of the filter modules. Following the rising edge of the MFE bit, the integrator will begin to
accumulate data in all four modules. When the same data output rate is used on all sinc filters, synchronous
timing is achieved.
Meeting or exceeding the maximum values will trigger an integrator overflow (IOx goes high). This overflow
condition is only possible in Oversampling Mode when the sinc filter is set to a Sinc
3
structure and it outputs only
full-scale values.
In Sample-and-Hold Mode, the integrator flag will go high if the maximum integrator value is exceeded
( – 2,147,483,648 or 2,147,483,648). This event will occur if the sample-and-hold signal SHx is held in the active
state longer than the overflow time.
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