Datasheet
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20
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140
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10
10G
Frequency(Hz)
Magnitude(dB)
100 1k 10k 100k 1G
V
REF
X
4
X
6
Integrator2
Comparator
f
CLK
DATA
DAC
X
3
X
2
X
(t)
f
S
Integrator1
AMC1204
AMC1204B
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SBAS512D –APRIL 2011–REVISED DECEMBER 2013
MODULATOR
The modulator topology of the AMC1204 and AMC1204B is fundamentally a second-order, switched-capacitor,
ΔΣ modulator, such as the one conceptualized in Figure 43. The analog input voltage (X
(t)
) and the output of the
1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage (X
2
) at the input of the first
integrator or modulator stage. The output of the first integrator is further differentiated with the DAC output; the
resulting voltage (X
3
) feeds the input of the second integrator stage. When the value of the integrated signal (X
4
)
at the output of the second stage equals the comparator reference voltage, the output of the comparator
switches from high to low, or vice versa, depending on its previous state. In this case, the 1-bit DAC responds on
the next clock pulse by changing its analog output voltage (X
6
), causing the integrators to progress in the
opposite direction, while forcing the value of the integrator output to track the average of the input.
Figure 43. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 44 ; therefore, a low-pass
digital filter should be used at the output of the device to increase the overall performance. This filter is also used
to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate
(decimation). A digital signal processor (DSP), microcontroller (µC), or field programmable gate array (FPGA)
can be used to implement the filter. Another option is to use a suitable application-specific device such as the
AMC1210, a four-channel digital sinc-filter.
Figure 44. Quantization Noise Shaping
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