Datasheet

V
REF
X
4
X
6
Integrator2
Comparator
f
CLK
DATA
DAC
X
3
X
2
X
(t)
f
S
Integrator1
AMC1203
SBAS427C –FEBRUARY 2008– REVISED JUNE 2011 www.ti.com
THEORY OF OPERATION
The differential analog input of the AMC1203 is There are two restrictions on the analog input signals,
implemented with a switched-capacitor circuit. This V
IN+
and V
IN–
. If the input voltage exceeds the range
switched-capacitor circuit implements a 2nd-order GND – 0.3V to V
DD
+ 0.3V, the input current must be
modulator stage that digitizes the input signal into a limited to 10mA, because the input protection diodes
1-bit output stream. The internally-generated clock on the front end of the converter begin to turn on. In
signal (sourcing the capacitor circuit and the addition, the linearity and the noise performance of
modulator) is available as an output signal on the the device is ensured only when the differential
MCLK pin. The analog input signal is continuously analog voltage resides within ±280mV.
sampled by the modulator and compared to an
internal voltage reference. A digital stream, accurately
MODULATOR
representing the analog input voltage over time,
The modulator topology of the AMC1203 is
appears at the output of the converter.
fundamentally a 2nd-order, switched-capacitor,
delta-sigma modulator, such as the one
ANALOG INPUT
conceptualized in Figure 24. The analog input voltage
The input design topology of the AMC1203 is based (X
(t)
) and the output of the 1-bit digital-to-analog
on a fully-differential, switched-capacitor architecture converter (DAC) are differentiated, providing an
with a dynamic input impedance of 28kΩ at 10MHz, analog voltage (X
2
) at the input of the first integrator
as Figure 1 shows. This input stage provides the or modulator stage. The output of the first integrator
mechanism to achieve low system noise, high is further differentiated with the DAC output, and the
common-mode rejection (92dB), and excellent resulting voltage (X
3
) feeds the input of the second
power-supply rejection. integrator stage. When the value of the integrated
signal (X
4
) at the output of the second stage equals
The input impedance becomes a consideration in
the comparator reference voltage, the output of the
designs with high input-signal source impedance.
comparator switches from high to low, or vice versa,
This high-impedance may cause degradation in gain,
depending on its previous state. In this case, the 1-bit
linearity, and THD. The importance of this effect,
DAC responds on the next clock pulse by changing
however, depends on the desired system
its analog output voltage (X
6
), causing the integrators
performance.
to progress in the opposite direction, while forcing the
value of the integrator output to track the average of
the input.
Figure 24. Block Diagram of the 2nd-Order Modulator
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