Datasheet

Device

VDDS_DPLL_MPU_USBHOST

Power Rail

DPLL4

DPLL1

DPLL3

VDDS_DPLL_PER_CORE

DPLL5

030-016

AM3517, AM3505

www.ti.com

SPRS550E –OCTOBER 2009–REVISED MARCH 2013

4.4 DPLL Specifications

The AM3517/05 integrates four DPLLs. The PRM and CM drive them.

The four main DPLLs are:

• DPLL1 (MPU)

• DPLL3 (Core)

• DPLL4 (Peripherals)

• DPLL5 (Second Peripherals DPLL)

Figure 4-6 illustrates the DPLL implementation.

Figure 4-6. DPLL Implementation

4.4.1 Digital Phase-Locked Loop (DPLL)

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the

AM3517/05 device.

DPLL1 gets an always-on clock used to produce the synthesized clock. They get a high-speed bypass

clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor

power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes

performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,

all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the AM3517/05 device have following features:

• Independent power domain per DPLL

• Controlled by clock-manager (CM)

• Fed with always-on system clock with independent gating control per DPLL

• Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-

MHz noise

• Up to four independent output dividers for simultaneous generation of multiple clock frequencies

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