Datasheet
sys_clkout1
CO0 CO1 CO1
030-014
AM3517, AM3505
www.ti.com
SPRS550E –OCTOBER 2009–REVISED MARCH 2013
4.3 Output Clock Specifications
Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:
• sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or
externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted
to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity
of sys_clkout1 is programmable.
• sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54
MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active
only when the core domain is active.
Table 4-7 summarizes the sys_clkout1 output clock electrical characteristics.
Table 4-7. SYS_CLKOUT1 Output Clock Electrical Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f Frequency 26 MHz
C
I
Load capacitance
(1)
f(max) = 38.4 MHz 70 pF
f(max) = 26 MHz 125
(1) The load capacitance is adapted to a frequency.
Table 4-8 details the sys_clkout1 output clock timing characteristics.
Table 4-8. SYS_CLKOUT1 Output Clock Switching Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f 1 / CO0 Frequency 26 MHz
CO1 t
w(CLKOUT1)
Pulse duration, sys_clkout1 low or high 0.40 * 0.60 * ns
t
c(CLKOUT1)
t
c(CLKOUT1)
CO2 t
R(CLKOUT1)
Rise time, sys_clkout1
(1)
3.31 ns
CO3 t
F(CLKOUT1)
Fall time, sys_clkout1
(1)
3.31 ns
(1) With a load capacitance of 25 pF.
Figure 4-4. SYS_CLKOUT1 System Output Clock
Table 4-9 summarizes the sys_clkout2 output clock electrical characteristics.
Table 4-9. SYS_CLKOUT2 Output Clock Electrical Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
f Frequency, sys_clkout2
(1)
166 MHz
C
L
Load capacitance
(2)
f(max) = 166 MHz 2 8 12 pF
(1) The maximum frequency supported is core_clk/2 MHz.
(2) The load capacitance is adapted to a frequency.
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