Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION[2] TYPE[3] ZCN BALL[4] ZER BALL[4] SUBSYSTEM PIN
MULTIPLEXING [5]
gpmc_nadv_ale Address Valid or O R1 AA14
Address Latch
Enable
gpmc_noe Output Enable O R2 AB14
gpmc_nwe Write Enable O R3 AA15
gpmc_nbe0_cle Lower Byte Enable. O R4 W11
Also used for
Command Latch
Enable
gpmc_nbe1 Upper Byte Enable O T1 Y15
gpmc_nwp Flash Write Protect O T2 W14
gpmc_wait0 External indication of I T3 V13
wait
gpmc_wait1 External indication of I T4 AA16
wait
gpmc_wait2 External indication of I T5 Y14
wait
gpmc_wait3 External indication of I U1 V14
wait
Table 2-5. External Memory Interfaces - SDRC Signals Description
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sdrc_d0 SDRAM data bit 0 IO B21 E3
sdrc_d1 SDRAM data bit 1 IO A21 D3
sdrc_d2 SDRAM data bit2 IO D20 C3
sdrc_d3 SDRAM data bit 3 IO C20 C2
sdrc_d4 SDRAM data bit 4 IO E19 F3
sdrc_d5 SDRAM data bit 5 IO D19 D2
sdrc_d6 SDRAM data bit 6 IO C19 C1
sdrc_d7 SDRAM data bit 7 IO B19 D1
sdrc_d8 SDRAM data bit 8 IO B18 G2
sdrc_d9 SDRAM data bit 9 IO D17 G3
sdrc_d10 SDRAM data bit 10 IO C17 H3
sdrc_d11 SDRAM data bit 11 IO D16 G4
sdrc_d12 SDRAM data bit 12 IO C16 H4
sdrc_d13 SDRAM data bit 13 IO B16 G1
sdrc_d14 SDRAM data bit 14 IO A16 J3
sdrc_d15 SDRAM data bit 15 IO A15 J1
sdrc_d16 SDRAM data bit 16 IO A7 T3
sdrc_d17 SDRAM data bit 17 IO B7 U3
sdrc_d18 SDRAM data bit 18 IO D7 U4
sdrc_d19 SDRAM data bit 19 IO E7 V4
sdrc_d20 SDRAM data bit 20 IO C6 V1
sdrc_d21 SDRAM data bit 21 IO D6 V2
sdrc_d22 SDRAM data bit 22 IO B5 V5
sdrc_d23 SDRAM data bit 23 IO C5 V3
sdrc_d24 SDRAM data bit 24 IO B4 W3
sdrc_d25 SDRAM data bit 25 IO A3 W4
sdrc_d26 SDRAM data bit 26 IO B3 Y3
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