Datasheet

jtag_tck
jtag_rtck
jtag_tdi
jtag_tms
jtag_emux(IN)
jtag_tdo
jtag_emux(OUT)
JT7
JT11
JT1
JT2 JT3
JT8
JT10JT9
JT4
JT5 JT6
JT12 JT13
JT14
030-113
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
In jtag_emux, x is equal to 0 to 1.
Figure 6-73. JTAG Interface Timing Free Running Clock Mode
6.8.2.2 JTAG Adaptive Clock Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-158. JTAG Timing Conditions Adaptive Clock Mode
1.8 V 3.3 V
TIMING CONDITION PARAMETER UNIT
MAX MAX
Input Conditions
t
R
Input signal rise time 5 3 ns
t
F
Input signal fall time 5 3 ns
Output Conditions
C
LOAD
Output load capacitance 30 pF
Table 6-159. JTAG Timing Requirements Adaptive Clock Mode
(1)(2)
1.8 V 3.3 V
NO. PARAMETER MIN MAX MIN MAX UNIT
JA4 t
c(tck)
Cycle time 20 20 ns
JA5 t
w(tckL)
Typical pulse duration, jtag_tck low 10 10 ns
JA6 t
w(tckH)
Typical pulse duration, jtag_tck high 10 10 ns
t
dc(lclk)
Duty cycle error, jtag_tck -2500 2500 -2500 2500 ps
t
j(lclk)
Cycle jitter -1500 1500 -1500 1500 ps
JA7 t
su(tdiV-tckH)
Setup time, jtag_tdi valid before jtag_tck high 13.8 13.8 ns
JA8 t
h(tdiV-tckH)
Hold time, jtag_tdi valid after jtag_tck high 13.8 13.8 ns
JA9 t
su(tmsV-tckH)
Setup time, jtag_tms valid before jtag_tck high 13.8 13.8 ns
JA10 t
h(tmsV-tckH)
Hold time, jtag_tms valid after jtag_tck high 13.8 13.8 ns
(1) Maximum cycle jitter supported by jtag _tck input clock.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 213
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