Datasheet

etk_clk
etk_ctl
etk_d[15:0]
ETM0
ETM2
ETM3
ETM2
ETM1
ETM3
030-110
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.8 Test Interfaces
The emulation and trace interfaces allow tracing activities of the following CPUs:
• ARM Cortex
TM
-A8 through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time
trace of the ARM subsystem operations.
All processors can be emulated via JTAG ports.
6.8.1 Embedded Trace Macro Interface (ETM)
The following tables assume testing over the recommended operating conditions.
Table 6-154. Embedded Trace Macro Interface Switching Characteristics
NO. PARAMETER MIN MAX UNIT
f 1/t
c(CLK)
Frequency, etk_clk 166 MHz
ETM0 t
c(CLK)
Cycle time 6.02 ns
ETM1 t
W(CLK)
Clock pulse width, etk_clk 3.01 ns
ETM2 t
d(CLK-CTL)
Delay time, etk_clk clock edge to etk_ctl transition -0.5 0.5 ns
ETM3 t
d(CLK-D)
Delay time, etk_clk clock high to etk_d[15:0] transition -0.5 0.5 ns
Figure 6-72. Embedded Trace Macro Interface
6.8.2 JTAG Interfaces
AM3517/05 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define
the timing requirements for several tools used to test the AM3517/05 processors as:
• Free running clock tool, like XDS560 and XDS510 tools
• Adaptive clock tool, like RealView ICE tool and Lauterbach tool
6.8.2.1 JTAG Free Running Clock Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-155. JTAG Timing Conditions Free Running Clock Mode
1.8 V 3.3 V
TIMING CONDITION PARAMETER UNIT
MAX MAX
Input Conditions
t
R
Input signal rise time 5 3 ns
t
F
Input signal fall time 5 3 ns
Output Conditions
C
LOAD
Output load capacitance 30 pF
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 211
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