Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-150. MMC/SD/SDIO Timing Requirements Standard SD Mode
(1)(2)(3)
NO. PARAMETER 1.8 V, 3.3V UNIT
MIN MAX
Standard SD Mode
MMC/SD/SDIO Interface 1
SD3 t
su(CMDV-CLKIH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock 6.23 ns
edge
SD4 t
h(CLKIH-CMDIV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock 19.37 ns
edge
SD7 t
su(DATxV-CLKIH)
Setup time, mmc1_datx valid before mmc1_clk rising clock 6.23 ns
edge
SD8 t
h(CLKIH-DATxIV)
Hold time, mmc1_datx valid after mmc1_clk rising clock 19.37 ns
edge
MMC/SD/SDIO Interface 2
SD3 t
su(CMDV-CLKIH)
Setup time, mmc2_cmd valid before mmc2_clk rising clock 6.23 ns
edge
SD4 t
h(CLKIH-CMDIV)
Hold time, mmc2_cmd valid after mmc2_clk rising clock 19.37 ns
edge
SD7 t
su(DATxV-CLKIH)
Setup time, mmc2_datx valid before mmc2_clk rising clock 6.23 ns
edge
SD8 t
h(CLKIH-DATxIV)
Hold time, mmc2_datx valid after mmc2_clk rising clock 19.37 ns
edge
MMC/SD/SDIO Interface 3
SD3 t
su(CMDV-CLKIH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock 6.23 ns
edge
SD4 t
h(CLKIH-CMDIV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock 19.37 ns
edge
SD7 t
su(DATxV-CLKIH)
Setup time, mmc3_datx valid before mmc3_clk rising clock 6.23 ns
edge
SD8 t
h(CLKIH-DATxIV)
Hold time, mmc3_datx valid after mmc3_clk rising clock 19.37 ns
edge
(1) Timing parameters refer to output clock specified in Table 6-151.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-151.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode
(1)(2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
Standard SD Mode
SD1 t
c(clk)
Cycle time 41.67 ns
SD2 t
W(clkH)
Typical pulse duration, output clk high X
(3)
*PO
(4)
ns
SD2 t
W(clkL)
Typical pulse duration, output clk low Y
(5)
*PO
(4)
ns
t
dc(clk)
Duty cycle error, output clk 2083.33 ps
t
j(clk)
Jitter standard deviation 200 ps
MMC/SD/SDIO Interface 1
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
(1) The jitter probability density can be approximated by a Gaussian function.
(2) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(3) The X parameter is defined as shown in Table 6-152.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown in Table 6-153.
208 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505