Datasheet

mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
HSSD5 HSSD5
HSSD6 HSSD6
HSSD1 HSSD2
030-107
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
HSSD3
HSSD7
HSSD4
HSSD8
HSSD1 HSSD2
030-106
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode
(1)(2)
(continued)
NO. PARAMETER 1.8 V, 3.3 V UNIT
MIN MAX
HSSD5 t
d(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to mmc2_cmd 3.72 14.11 ns
transition
HSSD6 t
d(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to mmc2_datx 3.72 14.11 ns
transition
MMC/SD/SDIO Interface 3
t
r(clk)
Rise time, output clk 3 ns
t
f(clkH)
Fall time, output clk 3 ns
t
r(clkL)
Rise time, output data 3 ns
t
f(clk)
Fall time, output data 3 ns
HSSD5 t
d(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to mmc3_cmd 3.72 14.11 ns
transition
HSSD6 t
d(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to mmc3_datx 3.72 14.11 ns
transition
Table 6-147. X Parameters
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
Table 6-148. Y Parameters
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference
Manual (literature number SPRUGR0).
In mmcx, x is equal to 1, 2, or 3.
Figure 6-68. MMC/SD/SDIO High-Speed SD Mode Data/Command Receive
In mmcx, x is equal to 1, 2, or 3.
Figure 6-69. MMC/SD/SDIO High-Speed SD Mode Data/Command Transmit
206 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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