Datasheet

mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
MMC5 MMC5
MMC6 MMC6
MMC1 MMC2
030-105
mmcx_clk
mmcx_cmd
mmcx_dat[3:0]
MMC3
MMC7
MMC4
MMC8
MMC1 MMC2
030-104
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
For details about clock division factor CLKD, see the AM35x ARM Microprocessor Technical Reference
Manual (literature number SPRUGR0).
In mmcx, x is equal to 1, 2, or 3.
Figure 6-66. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive
In mmcx, x is equal to 1, 2, or 3.
Figure 6-67. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Transmit
6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-144. MMC/SD/SDIO Timing Conditions High-Speed SD Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
High-Speed SD Mode
Input Conditions
t
R
Input signal rise time 0.19 3 ns
t
F
Input signal fall time 0.19 3 ns
Output Conditions
C
LOAD
Output load capacitance 30 pF
Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode
(1)(2)(3)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
High-Speed SD Mode
MMC/SD/SDIO Interface 1
HSSD3 t
su(CMDV-CLKIH)
Setup time, mmc1_cmd valid before mmc1_clk rising 5.61 ns
clock edge
HSSD4 t
h(CLKIH-CMDIV)
Hold time, mmc1_cmd valid after mmc1_clk rising 2.28 ns
clock edge
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-146.
(3) Timing Parameters refer to output clock specified in Table 6-146.
204 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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