Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification
Mode
(1)(2)
(continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
t
dc(clk)
Duty cycle error, output clk 2604.17 ps
t
j(clk)
Jitter standard deviation 200 ps
MMC/SD/SDIO Interface 1
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
MMC5 t
d(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to mmc1_cmd 4.3 47.78 ns
transition
MMC6 t
d(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to mmc1_datx 4.3 47.78 ns
transition
MMC/SD/SDIO Interface 2
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
MMC5 t
d(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to mmc2_cmd 4.3 47.78 ns
transition
MMC6 t
d(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to mmc2_datx 4.3 47.78 ns
transition
MMC/SD/SDIO Interface 3
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
MMC5 t
d(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to mmc3_cmd 4.3 47.78 ns
transition
MMC6 t
d(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to mmc3_datx 4.3 47.78 ns
transition
Table 6-142. X Parameter
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
Table 6-143. Y Parameter
CLKD Y
1 or Even 0.5
Odd (trunc[CLKD/2])/CLKD
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 203
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