Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode
(1) (2) (3)(4)
(continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSSD4/SD4 t
su(CLKIH-CMDIV)
Hold time, mmc2_cmd valid after mmc2_clk rising 1249.2 ns
clock edge
MMC/SD/SDIO Interface 3
HSSD3/SD3 t
su(CMDV-CLKIH)
Setup time, mmc3_cmd valid before mmc3_clk rising 1198.4 ns
clock edge
HSSD4/SD4 t
su(CLKIH-CMDIV)
Hold time, mmc3_cmd valid after mmc3_clk rising 1249.2 ns
clock edge
Table 6-131. MMC/SD/SDIO Switching Characteristics SD Identification Mode
(1)(2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD Identification Mode
HSSD1/SD1 t
c(clk)
Cycle time, output clk period 2500 ns
HSSD2/SD2 t
W(clkH)
Typical pulse duration, output clk high X
(3)
*PO
(4)
ns
HSSD2/SD2 t
W(clkL)
Typical pulse duration, output clk low Y
(5)
*PO
(4)
ns
t
dc(clk)
Duty cycle error, output clk 125 ns
t
j(clk)
Jitter standard deviation, output clk 200 ps
MMC/SD/SDIO Interface 1
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
HSSD5/SD5 t
d(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to mmc1_cmd 6.3 2492.7 ns
transition
MMC/SD/SDIO Interface 2
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
HSSD5/SD5 t
d(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to mmc2_cmd 6.3 2492.7 ns
transition
MMC/SD/SDIO Interface 3
t
r(clk)
Rise time, output clk 10 ns
t
f(clkH)
Fall time, output clk 10 ns
t
r(clkL)
Rise time, output data 10 ns
t
f(clk)
Fall time, output data 10 ns
HSSD5/SD5 t
d(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to mmc3_cmd 6.3 2492.7 ns
transition
(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown below.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown below.
Table 6-132. X Parameter
CLKD X
1 or Even 0.5
Odd (trunc[CLKD/2]+1)/CLKD
198 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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