Datasheet
AM3517, AM3505
www.ti.com
SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.7 Removable Media Interfaces
6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing
The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory
cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The
MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding
CRC, start/end bit, and checking for syntactical correctness.
There are three MMC interfaces on the AM3517/05:
• MMC/SD/SDIO Interface 1:
– 1.8-V/3.3-V support
– 8 bits
• MMC/SD/SDIO Interface 2:
– 1.8-V/3.3-V support
– 8 bits
– 4 bits with external transceiver allowing to support 1.8-V/3.3-V peripherals in 1.8-V mode operation.
Transceiver direction control signals are multiplexed with the upper four data bits.
• MMC/SD/SDIO Interface 3:
– 1.8-V/3.3-V support
– 8 bits
6.7.1.1 MMC/SD/SDIO in SD Identification Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-129. MMC/SD/SDIO Timing Conditions SD Identification Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD Identification Mode
Input Conditions
t
r
Input signal rise time 10 ns
t
f
Input signal fall time 10 ns
Output Conditions
C
LOAD
Output load capacitance 30 pF
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode
(1) (2) (3)(4)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
SD Identification Mode
MMC/SD/SDIO Interface 1
HSSD3/SD3 t
su(CMDV-CLKIH)
Setup time, mmc1_cmd valid before mmc1_clk rising 1198.4 ns
clock edge
HSSD4/SD4 t
su(CLKIH-CMDIV)
Hold time, mmc1_cmd valid after mmc1_clk rising 1249.2 ns
clock edge
MMC/SD/SDIO Interface 2
HSSD3/SD3 t
su(CMDV-CLKIH)
Setup time, mmc2_cmd valid before mmc2_clk rising 1198.4 ns
clock edge
(1) Timing parameters refer to output clock specified in Table 6-131.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-131.
(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).
(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 197
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