Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.6.11 I
2
C Interface
The multimaster I
2
C peripheral provides an interface between two or more devices via an I
2
C serial bus.
The I
2
C controller supports the multimaster mode which allows more than one device capable of
controlling the bus to be connected to it. Each I
2
C device is recognized by a unique address and can
operate as either transmitter or receiver, according to the function of the device. In addition to being a
transmitter or receiver, a device connected to the I
2
C bus can also be considered as master or slave when
performing data transfers. This data transfer is carried out via two serial bidirectional wires:
• An SDA data line
• An SCL clock line
The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing
format. The I
2
C interface is compliant with Philips I
2
C specification version 2.1. It supports standard mode
(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .
6.6.11.1 I
2
C Standard/Fast-Speed Mode
Table 6-126. I
2
C Standard/Fast-Speed Mode Timings
1.8V, 3.3-V
NO. PARAMETER
(1)
STANDARD FAST MODE UNIT
MODE
MIN MAX MIN MAX
f
SCL
Clock Frequency, i2cX_scl 100 400 kHz
I1 t
w(SCLH)
Pulse Duration, i2cX_scl high 4 0.6 s
I2 t
w(SCLL)
Pulse Duration, i2cX_scl low 4.7 1.3 s
I3 t
su(SDAV-SCLH)
Setup time, i2cX_sda valid before i2cX_scl active level 250 100
(2)
ns
I4 t
h(SCLHSDAV)
Hold time, i2cX_sda valid after i2cX_scl active level 3.45
(3)
0.9
(3)
s
I5 t
su(SDAL-SCLH)
Setup time, i2cX_scl high after i2cX_sda low (for a 4.7 0.6 s
START
(4)
condition or a repeated START condition)
I6 t
h(SCLHSDAH)
Hold time, i2cX_sda low level after i2cX_scl high level 4 0.6 s
(STOP condition)
I7 t
h(SCLHRSTART)
Hold time, i2cX_sda low level after i2cX_scl high level (for 4 0.6 s
a repeated START condition)
I8 t
w(SDAH)
Pulse duration, i2cX_sda high between STOP and START 4.7 1.3 s
conditions
t
R(SCL)
Rise time, i2cX_scl 1000 300 ns
t
F(SCL)
Fall time, i2cX_scl 300 300 ns
t
R(SDA)
Rise time, i2cX_sda 1000 300 ns
t
F(SDA)
Fall time, i2cX_sda 300 300 ns
CB Capacitive load for each bus line 60 60 pF
(1) In i2cX, X is equal to 1, 2, or 3.
(2) A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
su(SDAV-SCLH)
250 ns must then be
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low
period of the i2cx_scl, it must output the next data bit to the i2cx_sda line t
r(SDA)
max + t
su(SDAV-SCLH)
= 1000 + 250 = 1250 ns (according
to the standard-mode I
2
C-bus specification) before the i2cx_scl line is released.
(3) The maximum t
h(SCLH-SDA)
has only to be met if the device does not stretch the low period of the i2cx_scl signal.
(4) After this time, the first clock is generated.
194 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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