Datasheet

MD_CLK
MDIO_D
(output)
7
1
MD_CLK
MDIO_D
(input)
4
5
1
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.6.8 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
6.6.8.1 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-115. Timing Requirements for MDIO Input (see Figure 6-53 and Figure 6-54)
No. PARAMETER UNIT
MIN MAX
1 t
c(MD_CLK)
Cycle time, MD_CLK 400 ns
4 t
su(MDIO-MDCLKH)
Setup time, MDIO data input valid before MD_CLK high 20 ns
5 t
h(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high 0 ns
Figure 6-53. MDIO Input Timing
Table 6-116. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-54)
No. PARAMETER UNIT
MIN MAX
7 t
d(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid 0 100 ns
Figure 6-54. MDIO Output Timing
6.6.9 Universal Asynchronous Receiver/Transmitter (UART)
The AM3517/05 has four UARTs (one with Infrared Data Association [IrDA] and Consumer Infrared [CIR]
modes).
188 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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