Datasheet
mmx_txen_n
mmx_txdat
mmx_txse0
FSU23
FSU21
FSU22
FSU19
FSU19
FSU20
FSU20
FSU24
FSU25
Transmit
Receive
030-082
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013
www.ti.com
Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin
Mode (continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
FSU24 t
d(DATI-TXENH)
Delay time, mmx_txdat invalid to mmx_txen_n high 81.8 ns
FSU25 t
d(SE0I-TXENH)
Delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 ns
t
R(do)
Rise time, mmx_txen_n 4.0 ns
t
F(do)
Fall time, mmx_txen_n 4.0 ns
t
R(do)
Rise time, mmx_txdat 4.0 ns
t
F(do)
Fall time, mmx_txdat 4.0 ns
t
R(do)
Rise time, mmx_txse0 4.0 ns
t
F(do)
Fall time, mmx_txse0 4.0 ns
In mmx, x is equal to 0, 1, or 2.
Figure 6-49. Low-/Full-Speed USB Bidirectional Standard 3-pin Mode
6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing
In addition to the full-speed USB controller, a high-speed (HS) USB controller is instantiated inside the
AM3517/05. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 1 and 2.
• Port 1 and port 2:
– 12-bit master mode (SDR)
6.6.4.1 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit Master Mode
The following tables assume testing over the recommended operating conditions.
Table 6-107. High-Speed USB Timing Conditions 12-bit Master Mode
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
Input Conditions
t
R
Input signal rise time 2 ns
t
F
Input signal fall time 2 ns
Output Conditions
C
LOAD
Output load capacitance 3 pF
Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode
(1)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSU3 t
s(DIRV-CLKH)
Setup time, hsusbx_dir valid before hsusbx_clk rising edge 7.5 ns
t
s(NXTV-CLKH)
Setup time, hsusbx_nxt valid before hsusbx_clk rising edge 7.5 ns
HSU4 t
h(CLKH-DIRIV)
Hold time, hsusbx_dir valid after hsusbx_clk rising edge 0.2 ns
(1) In hsusbx, x is equal to 1 or 2.
182 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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