Datasheet

mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3
Bitn-4
Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
SM5 SM6
SM4
SM3
SM1
SM0
SM2
SM1
SM0
SM5 SM6
SM3
SM1
SM0
SM1
SM0
SM2
SM4
SM7
Mode0&2
Mode1&3
030-077
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Figure 6-46. McSPI Interface Transmit and Receive in Master Mode(1) (2) (3)
(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.
(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.
178 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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