Datasheet
AM3517, AM3505
www.ti.com
SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-97. McSPI3 Interface Switching Characteristics – Master Mode
(1) (2) (3)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM0 t
c(CLK)
Cycle time, mcspix_clk 41.67 41.67 ns
tj(CLK) Cycle jitter
(4)
-200 200 -200 200 ps
SM1 t
w(CLK)
Pulse duration, mcspix_clk high or low 0.45P
(5)
0.55P
(5)
0.45P
(5)
0.55P
(5)
ns
SM4 t
d(CLKAE-SIMOV)
Delay time, mcspix_clk active edge to -2.1 11.3 -3 ns
mcspix_simo shifted
SM5 t
d(CSnA-CLKFE)
Delay time, mcspix_csi active Modes 1 A
(6)
- 4.4 A
(6)
- 3.0 6 ns
to mcspix_clk first edge and 3
Modes 0 B
(7)
- 4.4 B
(7)
- 3.0 6 ns
and 2
SM6 t
d(CLKLE-CSnI)
Delay time, mcspix_clk last Modes 1 B
(7)
- 4.4 B
(7)
- 3.0 ns
edge to mcspix_csi inactive and 3
Modes 0 A
(6)
- 4.4 A
(6)
- 3.0 ns
and 2
SM7 t
d(CSnAE-SIMOV)
Delay time, mcspix_csi active Modes 0 11.3 5 ns
edge to mcspix_simo shifted and 2
(1) The capacitive load is equivalent to 20 pF.
(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and
mcspi3_somi is latched are all software configurable.
(3) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and
capture input data.
(4) Maximum cycle jitter supported by mcspix_clk input clock.
(5) P = mcspix_clk clock period.
(6) Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit
field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference
Guide [literature number SPRUFV6].
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port
Interface (McSPI) Reference Guide [literature number SPRUFV6].
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 177
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