Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-95. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode
(1) (2) (3)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM0 t
c(CLK)
Cycle time, mcspix_clk 20.83 20.83 ns
tj(CLK) Cycle jitter
(4)
, mcspix_clk -200 200 -200 200 ps
SM1 t
w(CLK)
Pulse duration, mcspix_clk high or low 0.45P
(5)
0.55P
(5)
0.45P
(5)
0.55P
(5)
ns
SM4 t
d(CLKAE-SIMOV)
Delay time, mcspix_clk active edge to -2.1 5 -3 6 ns
mcspix_simo shifted
SM5 t
d(CSnA-CLKFE)
Delay time, mcspix_csi active to Modes 1 A
(6)
- 3.2 A
(6)
- 3.0 6 ns
mcspix_clk first edge and 3
Modes 0 B
(7)
- 3.2 B
(7)
-3.0 6 ns
and 2
SM6 t
d(CLKLE-CSnI)
Delay time, mcspix_clk last edge to Modes 1 B
(7)
- 3.2 B
(7)
- 3.0 ns
mcspix_csi inactive and 3
Modes 0 A
(6)
- 3.2 A
(6)
- 3.0 ns
and 2
SM7 t
d(CSnAE-SIMOV)
Delay time, mcspix_csi active edge Modes 0 5 5 ns
to mcspix_simo shifted and 2
(1) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or
2, and 20 pF for spi4_clk and spi4_simo signals.
(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.
n is equal to 0 for x equal to 4.
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(4) Maximum cycle jitter supported by mcspix_clk input clock.
(5) P = mcspix_clk clock period
(6) Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a
bitfield of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference
Guide [literature number SPRUFV6].
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port
Interface (McSPI) Reference Guide [literature number SPRUFV6].
The following tables assume testing over the recommended operating conditions.
Table 6-96. McSPI 3 Interface Timing Requirements – Master Mode
(1) (2)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM2 t
su(SOMIV-CLKAE)
Setup time, mcspi3_somi valid before 2.5 4 ns
mcspi3_clk active edge
SM3 t
h(SOMIV-CLKAE)
Hold time, mcspi3_somi valid after mcspi3_clk 2.89 4 ns
active edge
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and
mcspi3_somi is latched is all software configurable.
176 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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