Datasheet

mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
mcspix_somi
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bitn-4 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
Bitn-1 Bitn-2 Bitn-3 Bit1 Bit0
SS4 SS5
SS6
SS3
SS1
SS0
SS2
SS1
SS0
SS4 SS5
SS3
SS1
SS0
SS1
SS0
SS2
SS6
SS7
Mode0&2
Mode1&3
030-076
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Figure 6-45. McSPI Interface Transmit and Receive in Slave Mode(1) (2)
(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.
6.6.2.2 McSPI in Master Mode
The following tables assume testing over the recommended operating conditions.
Table 6-94. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode
(1) (2)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SM2 t
su(SOMIV-CLKAE)
Setup time, mcspix_somi valid before mcspix_clk 2.56 4 ns
active edge
SM3 t
h(SOMIV-CLKAE)
Hold time, mcspix_somi valid after mcspix_clk active 2.93 4 ns
edge
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.
n is equal to 0 for x equal to 4.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 175
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