Datasheet
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013
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6.6.2 Multichannel Serial Port Interface (McSPI) Timing
The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four
peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following
timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and
any channel (n).
6.6.2.1 McSPI in Slave Mode
The following tables assume testing over the recommended operating conditions.
Table 6-92. McSPI Interface Timing Requirements – Slave Mode
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SS0 t
c(CLK)
Cycle time, mcspix_clk 41.67 41.67 ns
SS1 t
w(CLK)
Pulse duration, mcspix_clk high or low 18.75 22.92 11.25 ns
SS2 t
su(SIMOV-CLKAE)
Setup time, mcspix_simo valid before mcspix_clk 4.2 4 ns
active edge
SS3 t
h(SIMOV-CLKAE)
Hold time, mcspix_simo valid after mcspix_clk active 4.6 3 ns
edge
SS4 t
su(CS0V-CLKFE)
Setup time, mcspix_cs0 valid before mcspix_clk first 13.8 7 ns
edge
SS5 t
h(CS0I-CLKLE)
Hold time, mcspix_cs0 invalid after mcspix_clk last 13.8 9.17 ns
edge
Table 6-93. McSPI Interface Switching Characteristics
(1) (2) (3) (4)
NO. PARAMETER 1.8 V 3.3 V UNIT
MIN MAX MIN MAX
SS6 t
d(CLKAE-SOMIV)
Delay time, mcspix_clk active edge to mcspix_somi 1.8 15.9 2 16.5 ns
shifted
SS7 t
d(CS0AE-SOMIV)
Delay time, mcspix_cs0 active edge to Modes 0 and 2 16.38 15.9 ns
mcspix_somi shifted
(1) The capacitive load is equivalent to 20 pF.
(2) In mcspix, x is equal to 1, 2, 3, or 4.
(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
174 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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