Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.6.1.1.5 McBSP5
The following tables show the timing conditions and switching characteristics for McBSP5.
Table 6-81. McBSP5 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp5_dr Master
valid before
Half Cycle 7.7 7.7 ns
mcbsp5_clkx
Slave
active edge
Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 7.5 7.5 ns
DRV) mcbsp5_dr Master
valid after
Half Cycle 7.7 7.7 ns
mcbsp5_clkx
Slave
active edge
Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp5_fsx Slave
valid before
Full Cycle 5.8 5.8 ns
mcbsp5_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSV) mcbsp5_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp5_clkx
Slave
active edge
Table 6-82. McBSP5 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp5_clkx active 0.2 14.8 0.7 14.8 ns
FSXV) edge to mcbsp5_fsx valid
Table 6-83. McBSP5 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp5_fsx Slave
valid before
Full Cycle 5.8 5.8 ns
mcbsp5_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp5_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp5_clkx
Slave
active edge
Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp5_clkx
active edge to
mcbsp5_fsx
valid
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 169
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505