Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before
Full Cycle 4.2 4.2 ns
mcbsp3_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSV) mcbsp3_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp3_clkx
Slave
active edge
Table 6-66. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.2 14.8 ns
FSXV) mcbsp3_clkx
active edge to
mcbsp3_fsx
valid
Table 6-67. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 5.2 5.2 ns
CLKXAE) mcbsp3_fsx Slave
valid before
Full Cycle 4.2 4.2 ns
mcbsp3_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp3_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp3_clkx
Slave
active edge
Table 6-68. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp3_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp3_clkx
Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp3_dx
valid
Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKXAE) mcbsp3_dr Master
valid before
Half Cycle 5.2 5.2 ns
mcbsp3_clkx
Slave
active edge
Full Cycle 4.2 4.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
164 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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