Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-42. McBSP1 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV=3.3V VDDSHV=1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKAE-FSV) Delay time, 0.2 14.8 0.2 14.8 ns
mcbsp1_clkr
active edge to
mcbsp1_fsr /
mcbsp1_fsx
valid
Table 6-43. McBSP1 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Full Cycle 5.2 4.7 ns
CLKXAE) mcbsp1_fsx Slave
valid before
Half Cycle 4.2 3.7 ns
mcbsp1_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Full Cycle 5.2 4.7 ns
FSXV) mcbsp1_fsx Slave
valid after
Half Cycle 1.0 0.5 ns
mcbsp1_clkx
Slave
active edge
Table 6-44. McBSP1 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 14.8 0.7 14.8 ns
FSXV) mcbsp1_clkx
active edge to
mcbsp1_fsx
valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp1_clkx
Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp1_dx
valid
Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKAE) mcbsp1_dr Master
valid before
Half Cycle 5.2 5.2 ns
mcbsp1_clkr /
Slave
mcbsp1_clkx
active edge
Full Cycle 4.0 4.0 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp1_dr Master
valid after
Half Cycle 5.2 5.2 ns
mcbsp1_clkr /
Slave
mcbsp1_clkx
active edge
Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKAE) mcbsp1_fsr / Slave
mcbsp1_fsx
Full Cycle 4.2 4.2 ns
valid before
Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 157
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